efm32tg11b140_pac/vdac0/
opa2_timer.rs

1#[doc = "Register `OPA2_TIMER` reader"]
2pub struct R(crate::R<OPA2_TIMER_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<OPA2_TIMER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<OPA2_TIMER_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<OPA2_TIMER_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `OPA2_TIMER` writer"]
17pub struct W(crate::W<OPA2_TIMER_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<OPA2_TIMER_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<OPA2_TIMER_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<OPA2_TIMER_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `STARTUPDLY` reader - OPAx Startup Delay Count Value"]
38pub type STARTUPDLY_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `STARTUPDLY` writer - OPAx Startup Delay Count Value"]
40pub type STARTUPDLY_W<'a> = crate::FieldWriter<'a, u32, OPA2_TIMER_SPEC, u8, u8, 6, 0>;
41#[doc = "Field `WARMUPTIME` reader - OPAx Warmup Time Count Value"]
42pub type WARMUPTIME_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `WARMUPTIME` writer - OPAx Warmup Time Count Value"]
44pub type WARMUPTIME_W<'a> = crate::FieldWriter<'a, u32, OPA2_TIMER_SPEC, u8, u8, 7, 8>;
45#[doc = "Field `SETTLETIME` reader - OPAx Output Settling Timeout Value"]
46pub type SETTLETIME_R = crate::FieldReader<u16, u16>;
47#[doc = "Field `SETTLETIME` writer - OPAx Output Settling Timeout Value"]
48pub type SETTLETIME_W<'a> = crate::FieldWriter<'a, u32, OPA2_TIMER_SPEC, u16, u16, 10, 16>;
49impl R {
50    #[doc = "Bits 0:5 - OPAx Startup Delay Count Value"]
51    #[inline(always)]
52    pub fn startupdly(&self) -> STARTUPDLY_R {
53        STARTUPDLY_R::new((self.bits & 0x3f) as u8)
54    }
55    #[doc = "Bits 8:14 - OPAx Warmup Time Count Value"]
56    #[inline(always)]
57    pub fn warmuptime(&self) -> WARMUPTIME_R {
58        WARMUPTIME_R::new(((self.bits >> 8) & 0x7f) as u8)
59    }
60    #[doc = "Bits 16:25 - OPAx Output Settling Timeout Value"]
61    #[inline(always)]
62    pub fn settletime(&self) -> SETTLETIME_R {
63        SETTLETIME_R::new(((self.bits >> 16) & 0x03ff) as u16)
64    }
65}
66impl W {
67    #[doc = "Bits 0:5 - OPAx Startup Delay Count Value"]
68    #[inline(always)]
69    pub fn startupdly(&mut self) -> STARTUPDLY_W {
70        STARTUPDLY_W::new(self)
71    }
72    #[doc = "Bits 8:14 - OPAx Warmup Time Count Value"]
73    #[inline(always)]
74    pub fn warmuptime(&mut self) -> WARMUPTIME_W {
75        WARMUPTIME_W::new(self)
76    }
77    #[doc = "Bits 16:25 - OPAx Output Settling Timeout Value"]
78    #[inline(always)]
79    pub fn settletime(&mut self) -> SETTLETIME_W {
80        SETTLETIME_W::new(self)
81    }
82    #[doc = "Writes raw bits to the register."]
83    #[inline(always)]
84    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
85        self.0.bits(bits);
86        self
87    }
88}
89#[doc = "Operational Amplifier Timer Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opa2_timer](index.html) module"]
90pub struct OPA2_TIMER_SPEC;
91impl crate::RegisterSpec for OPA2_TIMER_SPEC {
92    type Ux = u32;
93}
94#[doc = "`read()` method returns [opa2_timer::R](R) reader structure"]
95impl crate::Readable for OPA2_TIMER_SPEC {
96    type Reader = R;
97}
98#[doc = "`write(|w| ..)` method takes [opa2_timer::W](W) writer structure"]
99impl crate::Writable for OPA2_TIMER_SPEC {
100    type Writer = W;
101}
102#[doc = "`reset()` method sets OPA2_TIMER to value 0x0001_0700"]
103impl crate::Resettable for OPA2_TIMER_SPEC {
104    #[inline(always)]
105    fn reset_value() -> Self::Ux {
106        0x0001_0700
107    }
108}
efm32tg11b140_pac/vdac0/opa2_timer.rs

efm32tg11b140_pac/vdac0/
opa2_timer.rs
