efm32tg11b140_pac/vdac0/
status.rs

1#[doc = "Register `STATUS` reader"]
2pub struct R(crate::R<STATUS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<STATUS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<STATUS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<STATUS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `CH0ENS` reader - Channel 0 Enabled Status"]
17pub type CH0ENS_R = crate::BitReader<bool>;
18#[doc = "Field `CH1ENS` reader - Channel 1 Enabled Status"]
19pub type CH1ENS_R = crate::BitReader<bool>;
20#[doc = "Field `CH0BL` reader - Channel 0 Buffer Level"]
21pub type CH0BL_R = crate::BitReader<bool>;
22#[doc = "Field `CH1BL` reader - Channel 1 Buffer Level"]
23pub type CH1BL_R = crate::BitReader<bool>;
24#[doc = "Field `CH0WARM` reader - Channel 0 Warm"]
25pub type CH0WARM_R = crate::BitReader<bool>;
26#[doc = "Field `CH1WARM` reader - Channel 1 Warm"]
27pub type CH1WARM_R = crate::BitReader<bool>;
28#[doc = "Field `OPA0APORTCONFLICT` reader - OPA0 Bus Conflict Output"]
29pub type OPA0APORTCONFLICT_R = crate::BitReader<bool>;
30#[doc = "Field `OPA1APORTCONFLICT` reader - OPA1 Bus Conflict Output"]
31pub type OPA1APORTCONFLICT_R = crate::BitReader<bool>;
32#[doc = "Field `OPA2APORTCONFLICT` reader - OPA2 Bus Conflict Output"]
33pub type OPA2APORTCONFLICT_R = crate::BitReader<bool>;
34#[doc = "Field `OPA3APORTCONFLICT` reader - OPA3 Bus Conflict Output"]
35pub type OPA3APORTCONFLICT_R = crate::BitReader<bool>;
36#[doc = "Field `OPA0ENS` reader - OPA0 Enabled Status"]
37pub type OPA0ENS_R = crate::BitReader<bool>;
38#[doc = "Field `OPA1ENS` reader - OPA1 Enabled Status"]
39pub type OPA1ENS_R = crate::BitReader<bool>;
40#[doc = "Field `OPA2ENS` reader - OPA2 Enabled Status"]
41pub type OPA2ENS_R = crate::BitReader<bool>;
42#[doc = "Field `OPA3ENS` reader - OPA3 Enabled Status"]
43pub type OPA3ENS_R = crate::BitReader<bool>;
44#[doc = "Field `OPA0WARM` reader - OPA0 Warm Status"]
45pub type OPA0WARM_R = crate::BitReader<bool>;
46#[doc = "Field `OPA1WARM` reader - OPA1 Warm Status"]
47pub type OPA1WARM_R = crate::BitReader<bool>;
48#[doc = "Field `OPA2WARM` reader - OPA2 Warm Status"]
49pub type OPA2WARM_R = crate::BitReader<bool>;
50#[doc = "Field `OPA3WARM` reader - OPA3 Warm Status"]
51pub type OPA3WARM_R = crate::BitReader<bool>;
52#[doc = "Field `OPA0OUTVALID` reader - OPA0 Output Valid Status"]
53pub type OPA0OUTVALID_R = crate::BitReader<bool>;
54#[doc = "Field `OPA1OUTVALID` reader - OPA1 Output Valid Status"]
55pub type OPA1OUTVALID_R = crate::BitReader<bool>;
56#[doc = "Field `OPA2OUTVALID` reader - OPA2 Output Valid Status"]
57pub type OPA2OUTVALID_R = crate::BitReader<bool>;
58#[doc = "Field `OPA3OUTVALID` reader - OPA3 Output Valid Status"]
59pub type OPA3OUTVALID_R = crate::BitReader<bool>;
60impl R {
61    #[doc = "Bit 0 - Channel 0 Enabled Status"]
62    #[inline(always)]
63    pub fn ch0ens(&self) -> CH0ENS_R {
64        CH0ENS_R::new((self.bits & 1) != 0)
65    }
66    #[doc = "Bit 1 - Channel 1 Enabled Status"]
67    #[inline(always)]
68    pub fn ch1ens(&self) -> CH1ENS_R {
69        CH1ENS_R::new(((self.bits >> 1) & 1) != 0)
70    }
71    #[doc = "Bit 2 - Channel 0 Buffer Level"]
72    #[inline(always)]
73    pub fn ch0bl(&self) -> CH0BL_R {
74        CH0BL_R::new(((self.bits >> 2) & 1) != 0)
75    }
76    #[doc = "Bit 3 - Channel 1 Buffer Level"]
77    #[inline(always)]
78    pub fn ch1bl(&self) -> CH1BL_R {
79        CH1BL_R::new(((self.bits >> 3) & 1) != 0)
80    }
81    #[doc = "Bit 4 - Channel 0 Warm"]
82    #[inline(always)]
83    pub fn ch0warm(&self) -> CH0WARM_R {
84        CH0WARM_R::new(((self.bits >> 4) & 1) != 0)
85    }
86    #[doc = "Bit 5 - Channel 1 Warm"]
87    #[inline(always)]
88    pub fn ch1warm(&self) -> CH1WARM_R {
89        CH1WARM_R::new(((self.bits >> 5) & 1) != 0)
90    }
91    #[doc = "Bit 16 - OPA0 Bus Conflict Output"]
92    #[inline(always)]
93    pub fn opa0aportconflict(&self) -> OPA0APORTCONFLICT_R {
94        OPA0APORTCONFLICT_R::new(((self.bits >> 16) & 1) != 0)
95    }
96    #[doc = "Bit 17 - OPA1 Bus Conflict Output"]
97    #[inline(always)]
98    pub fn opa1aportconflict(&self) -> OPA1APORTCONFLICT_R {
99        OPA1APORTCONFLICT_R::new(((self.bits >> 17) & 1) != 0)
100    }
101    #[doc = "Bit 18 - OPA2 Bus Conflict Output"]
102    #[inline(always)]
103    pub fn opa2aportconflict(&self) -> OPA2APORTCONFLICT_R {
104        OPA2APORTCONFLICT_R::new(((self.bits >> 18) & 1) != 0)
105    }
106    #[doc = "Bit 19 - OPA3 Bus Conflict Output"]
107    #[inline(always)]
108    pub fn opa3aportconflict(&self) -> OPA3APORTCONFLICT_R {
109        OPA3APORTCONFLICT_R::new(((self.bits >> 19) & 1) != 0)
110    }
111    #[doc = "Bit 20 - OPA0 Enabled Status"]
112    #[inline(always)]
113    pub fn opa0ens(&self) -> OPA0ENS_R {
114        OPA0ENS_R::new(((self.bits >> 20) & 1) != 0)
115    }
116    #[doc = "Bit 21 - OPA1 Enabled Status"]
117    #[inline(always)]
118    pub fn opa1ens(&self) -> OPA1ENS_R {
119        OPA1ENS_R::new(((self.bits >> 21) & 1) != 0)
120    }
121    #[doc = "Bit 22 - OPA2 Enabled Status"]
122    #[inline(always)]
123    pub fn opa2ens(&self) -> OPA2ENS_R {
124        OPA2ENS_R::new(((self.bits >> 22) & 1) != 0)
125    }
126    #[doc = "Bit 23 - OPA3 Enabled Status"]
127    #[inline(always)]
128    pub fn opa3ens(&self) -> OPA3ENS_R {
129        OPA3ENS_R::new(((self.bits >> 23) & 1) != 0)
130    }
131    #[doc = "Bit 24 - OPA0 Warm Status"]
132    #[inline(always)]
133    pub fn opa0warm(&self) -> OPA0WARM_R {
134        OPA0WARM_R::new(((self.bits >> 24) & 1) != 0)
135    }
136    #[doc = "Bit 25 - OPA1 Warm Status"]
137    #[inline(always)]
138    pub fn opa1warm(&self) -> OPA1WARM_R {
139        OPA1WARM_R::new(((self.bits >> 25) & 1) != 0)
140    }
141    #[doc = "Bit 26 - OPA2 Warm Status"]
142    #[inline(always)]
143    pub fn opa2warm(&self) -> OPA2WARM_R {
144        OPA2WARM_R::new(((self.bits >> 26) & 1) != 0)
145    }
146    #[doc = "Bit 27 - OPA3 Warm Status"]
147    #[inline(always)]
148    pub fn opa3warm(&self) -> OPA3WARM_R {
149        OPA3WARM_R::new(((self.bits >> 27) & 1) != 0)
150    }
151    #[doc = "Bit 28 - OPA0 Output Valid Status"]
152    #[inline(always)]
153    pub fn opa0outvalid(&self) -> OPA0OUTVALID_R {
154        OPA0OUTVALID_R::new(((self.bits >> 28) & 1) != 0)
155    }
156    #[doc = "Bit 29 - OPA1 Output Valid Status"]
157    #[inline(always)]
158    pub fn opa1outvalid(&self) -> OPA1OUTVALID_R {
159        OPA1OUTVALID_R::new(((self.bits >> 29) & 1) != 0)
160    }
161    #[doc = "Bit 30 - OPA2 Output Valid Status"]
162    #[inline(always)]
163    pub fn opa2outvalid(&self) -> OPA2OUTVALID_R {
164        OPA2OUTVALID_R::new(((self.bits >> 30) & 1) != 0)
165    }
166    #[doc = "Bit 31 - OPA3 Output Valid Status"]
167    #[inline(always)]
168    pub fn opa3outvalid(&self) -> OPA3OUTVALID_R {
169        OPA3OUTVALID_R::new(((self.bits >> 31) & 1) != 0)
170    }
171}
172#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
173pub struct STATUS_SPEC;
174impl crate::RegisterSpec for STATUS_SPEC {
175    type Ux = u32;
176}
177#[doc = "`read()` method returns [status::R](R) reader structure"]
178impl crate::Readable for STATUS_SPEC {
179    type Reader = R;
180}
181#[doc = "`reset()` method sets STATUS to value 0x0c"]
182impl crate::Resettable for STATUS_SPEC {
183    #[inline(always)]
184    fn reset_value() -> Self::Ux {
185        0x0c
186    }
187}
efm32tg11b140_pac/vdac0/status.rs

efm32tg11b140_pac/vdac0/
status.rs
