efm32tg11b140_pac/cmu/
hfbusclken0.rs1#[doc = "Register `HFBUSCLKEN0` reader"]
2pub struct R(crate::R<HFBUSCLKEN0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<HFBUSCLKEN0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<HFBUSCLKEN0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<HFBUSCLKEN0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `HFBUSCLKEN0` writer"]
17pub struct W(crate::W<HFBUSCLKEN0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<HFBUSCLKEN0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<HFBUSCLKEN0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<HFBUSCLKEN0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `LE` reader - Low Energy Peripheral Interface Clock Enable"]
38pub type LE_R = crate::BitReader<bool>;
39#[doc = "Field `LE` writer - Low Energy Peripheral Interface Clock Enable"]
40pub type LE_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 0>;
41#[doc = "Field `CRYPTO0` reader - Advanced Encryption Standard Accelerator Clock Enable"]
42pub type CRYPTO0_R = crate::BitReader<bool>;
43#[doc = "Field `CRYPTO0` writer - Advanced Encryption Standard Accelerator Clock Enable"]
44pub type CRYPTO0_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 1>;
45#[doc = "Field `GPIO` reader - General purpose Input/Output Clock Enable"]
46pub type GPIO_R = crate::BitReader<bool>;
47#[doc = "Field `GPIO` writer - General purpose Input/Output Clock Enable"]
48pub type GPIO_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 2>;
49#[doc = "Field `PRS` reader - Peripheral Reflex System Clock Enable"]
50pub type PRS_R = crate::BitReader<bool>;
51#[doc = "Field `PRS` writer - Peripheral Reflex System Clock Enable"]
52pub type PRS_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 3>;
53#[doc = "Field `LDMA` reader - Linked Direct Memory Access Controller Clock Enable"]
54pub type LDMA_R = crate::BitReader<bool>;
55#[doc = "Field `LDMA` writer - Linked Direct Memory Access Controller Clock Enable"]
56pub type LDMA_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 4>;
57#[doc = "Field `GPCRC` reader - General Purpose CRC Clock Enable"]
58pub type GPCRC_R = crate::BitReader<bool>;
59#[doc = "Field `GPCRC` writer - General Purpose CRC Clock Enable"]
60pub type GPCRC_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 5>;
61impl R {
62 #[doc = "Bit 0 - Low Energy Peripheral Interface Clock Enable"]
63 #[inline(always)]
64 pub fn le(&self) -> LE_R {
65 LE_R::new((self.bits & 1) != 0)
66 }
67 #[doc = "Bit 1 - Advanced Encryption Standard Accelerator Clock Enable"]
68 #[inline(always)]
69 pub fn crypto0(&self) -> CRYPTO0_R {
70 CRYPTO0_R::new(((self.bits >> 1) & 1) != 0)
71 }
72 #[doc = "Bit 2 - General purpose Input/Output Clock Enable"]
73 #[inline(always)]
74 pub fn gpio(&self) -> GPIO_R {
75 GPIO_R::new(((self.bits >> 2) & 1) != 0)
76 }
77 #[doc = "Bit 3 - Peripheral Reflex System Clock Enable"]
78 #[inline(always)]
79 pub fn prs(&self) -> PRS_R {
80 PRS_R::new(((self.bits >> 3) & 1) != 0)
81 }
82 #[doc = "Bit 4 - Linked Direct Memory Access Controller Clock Enable"]
83 #[inline(always)]
84 pub fn ldma(&self) -> LDMA_R {
85 LDMA_R::new(((self.bits >> 4) & 1) != 0)
86 }
87 #[doc = "Bit 5 - General Purpose CRC Clock Enable"]
88 #[inline(always)]
89 pub fn gpcrc(&self) -> GPCRC_R {
90 GPCRC_R::new(((self.bits >> 5) & 1) != 0)
91 }
92}
93impl W {
94 #[doc = "Bit 0 - Low Energy Peripheral Interface Clock Enable"]
95 #[inline(always)]
96 pub fn le(&mut self) -> LE_W {
97 LE_W::new(self)
98 }
99 #[doc = "Bit 1 - Advanced Encryption Standard Accelerator Clock Enable"]
100 #[inline(always)]
101 pub fn crypto0(&mut self) -> CRYPTO0_W {
102 CRYPTO0_W::new(self)
103 }
104 #[doc = "Bit 2 - General purpose Input/Output Clock Enable"]
105 #[inline(always)]
106 pub fn gpio(&mut self) -> GPIO_W {
107 GPIO_W::new(self)
108 }
109 #[doc = "Bit 3 - Peripheral Reflex System Clock Enable"]
110 #[inline(always)]
111 pub fn prs(&mut self) -> PRS_W {
112 PRS_W::new(self)
113 }
114 #[doc = "Bit 4 - Linked Direct Memory Access Controller Clock Enable"]
115 #[inline(always)]
116 pub fn ldma(&mut self) -> LDMA_W {
117 LDMA_W::new(self)
118 }
119 #[doc = "Bit 5 - General Purpose CRC Clock Enable"]
120 #[inline(always)]
121 pub fn gpcrc(&mut self) -> GPCRC_W {
122 GPCRC_W::new(self)
123 }
124 #[doc = "Writes raw bits to the register."]
125 #[inline(always)]
126 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
127 self.0.bits(bits);
128 self
129 }
130}
131#[doc = "High Frequency Bus Clock Enable Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfbusclken0](index.html) module"]
132pub struct HFBUSCLKEN0_SPEC;
133impl crate::RegisterSpec for HFBUSCLKEN0_SPEC {
134 type Ux = u32;
135}
136#[doc = "`read()` method returns [hfbusclken0::R](R) reader structure"]
137impl crate::Readable for HFBUSCLKEN0_SPEC {
138 type Reader = R;
139}
140#[doc = "`write(|w| ..)` method takes [hfbusclken0::W](W) writer structure"]
141impl crate::Writable for HFBUSCLKEN0_SPEC {
142 type Writer = W;
143}
144#[doc = "`reset()` method sets HFBUSCLKEN0 to value 0"]
145impl crate::Resettable for HFBUSCLKEN0_SPEC {
146 #[inline(always)]
147 fn reset_value() -> Self::Ux {
148 0
149 }
150}