efm32tg11b120_pac/ldma/
ch6_reqsel.rs

1#[doc = "Register `CH6_REQSEL` reader"]
2pub struct R(crate::R<CH6_REQSEL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH6_REQSEL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH6_REQSEL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH6_REQSEL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH6_REQSEL` writer"]
17pub struct W(crate::W<CH6_REQSEL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH6_REQSEL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH6_REQSEL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH6_REQSEL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH6_REQSEL_SPEC, u8, u8, 4, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Peripheral Reflex System"]
48    PRS = 1,
49    #[doc = "8: Analog to Digital Converter 0"]
50    ADC0 = 8,
51    #[doc = "10: Digital to Analog Converter 0"]
52    VDAC0 = 10,
53    #[doc = "12: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
54    USART0 = 12,
55    #[doc = "13: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
56    USART1 = 13,
57    #[doc = "14: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
58    USART2 = 14,
59    #[doc = "15: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
60    USART3 = 15,
61    #[doc = "18: Universal Asynchronous Receiver/Transmitter 0"]
62    UART0 = 18,
63    #[doc = "20: Low Energy UART 0"]
64    LEUART0 = 20,
65    #[doc = "22: I2C 0"]
66    I2C0 = 22,
67    #[doc = "23: I2C 1"]
68    I2C1 = 23,
69    #[doc = "25: Timer 0"]
70    TIMER0 = 25,
71    #[doc = "26: Timer 1"]
72    TIMER1 = 26,
73    #[doc = "32: Wide Timer 0"]
74    WTIMER0 = 32,
75    #[doc = "33: Wide Timer 1"]
76    WTIMER1 = 33,
77    #[doc = "48: Memory System Controller"]
78    MSC = 48,
79    #[doc = "49: Advanced Encryption Standard Accelerator"]
80    CRYPTO0 = 49,
81    #[doc = "61: Capacitive touch sense module"]
82    CSEN = 61,
83    #[doc = "62: Low Energy Sensor Interface"]
84    LESENSE = 62,
85}
86impl From<SOURCESEL_A> for u8 {
87    #[inline(always)]
88    fn from(variant: SOURCESEL_A) -> Self {
89        variant as _
90    }
91}
92#[doc = "Field `SOURCESEL` reader - Source Select"]
93pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
94impl SOURCESEL_R {
95    #[doc = "Get enumerated values variant"]
96    #[inline(always)]
97    pub fn variant(&self) -> Option<SOURCESEL_A> {
98        match self.bits {
99            0 => Some(SOURCESEL_A::NONE),
100            1 => Some(SOURCESEL_A::PRS),
101            8 => Some(SOURCESEL_A::ADC0),
102            10 => Some(SOURCESEL_A::VDAC0),
103            12 => Some(SOURCESEL_A::USART0),
104            13 => Some(SOURCESEL_A::USART1),
105            14 => Some(SOURCESEL_A::USART2),
106            15 => Some(SOURCESEL_A::USART3),
107            18 => Some(SOURCESEL_A::UART0),
108            20 => Some(SOURCESEL_A::LEUART0),
109            22 => Some(SOURCESEL_A::I2C0),
110            23 => Some(SOURCESEL_A::I2C1),
111            25 => Some(SOURCESEL_A::TIMER0),
112            26 => Some(SOURCESEL_A::TIMER1),
113            32 => Some(SOURCESEL_A::WTIMER0),
114            33 => Some(SOURCESEL_A::WTIMER1),
115            48 => Some(SOURCESEL_A::MSC),
116            49 => Some(SOURCESEL_A::CRYPTO0),
117            61 => Some(SOURCESEL_A::CSEN),
118            62 => Some(SOURCESEL_A::LESENSE),
119            _ => None,
120        }
121    }
122    #[doc = "Checks if the value of the field is `NONE`"]
123    #[inline(always)]
124    pub fn is_none(&self) -> bool {
125        *self == SOURCESEL_A::NONE
126    }
127    #[doc = "Checks if the value of the field is `PRS`"]
128    #[inline(always)]
129    pub fn is_prs(&self) -> bool {
130        *self == SOURCESEL_A::PRS
131    }
132    #[doc = "Checks if the value of the field is `ADC0`"]
133    #[inline(always)]
134    pub fn is_adc0(&self) -> bool {
135        *self == SOURCESEL_A::ADC0
136    }
137    #[doc = "Checks if the value of the field is `VDAC0`"]
138    #[inline(always)]
139    pub fn is_vdac0(&self) -> bool {
140        *self == SOURCESEL_A::VDAC0
141    }
142    #[doc = "Checks if the value of the field is `USART0`"]
143    #[inline(always)]
144    pub fn is_usart0(&self) -> bool {
145        *self == SOURCESEL_A::USART0
146    }
147    #[doc = "Checks if the value of the field is `USART1`"]
148    #[inline(always)]
149    pub fn is_usart1(&self) -> bool {
150        *self == SOURCESEL_A::USART1
151    }
152    #[doc = "Checks if the value of the field is `USART2`"]
153    #[inline(always)]
154    pub fn is_usart2(&self) -> bool {
155        *self == SOURCESEL_A::USART2
156    }
157    #[doc = "Checks if the value of the field is `USART3`"]
158    #[inline(always)]
159    pub fn is_usart3(&self) -> bool {
160        *self == SOURCESEL_A::USART3
161    }
162    #[doc = "Checks if the value of the field is `UART0`"]
163    #[inline(always)]
164    pub fn is_uart0(&self) -> bool {
165        *self == SOURCESEL_A::UART0
166    }
167    #[doc = "Checks if the value of the field is `LEUART0`"]
168    #[inline(always)]
169    pub fn is_leuart0(&self) -> bool {
170        *self == SOURCESEL_A::LEUART0
171    }
172    #[doc = "Checks if the value of the field is `I2C0`"]
173    #[inline(always)]
174    pub fn is_i2c0(&self) -> bool {
175        *self == SOURCESEL_A::I2C0
176    }
177    #[doc = "Checks if the value of the field is `I2C1`"]
178    #[inline(always)]
179    pub fn is_i2c1(&self) -> bool {
180        *self == SOURCESEL_A::I2C1
181    }
182    #[doc = "Checks if the value of the field is `TIMER0`"]
183    #[inline(always)]
184    pub fn is_timer0(&self) -> bool {
185        *self == SOURCESEL_A::TIMER0
186    }
187    #[doc = "Checks if the value of the field is `TIMER1`"]
188    #[inline(always)]
189    pub fn is_timer1(&self) -> bool {
190        *self == SOURCESEL_A::TIMER1
191    }
192    #[doc = "Checks if the value of the field is `WTIMER0`"]
193    #[inline(always)]
194    pub fn is_wtimer0(&self) -> bool {
195        *self == SOURCESEL_A::WTIMER0
196    }
197    #[doc = "Checks if the value of the field is `WTIMER1`"]
198    #[inline(always)]
199    pub fn is_wtimer1(&self) -> bool {
200        *self == SOURCESEL_A::WTIMER1
201    }
202    #[doc = "Checks if the value of the field is `MSC`"]
203    #[inline(always)]
204    pub fn is_msc(&self) -> bool {
205        *self == SOURCESEL_A::MSC
206    }
207    #[doc = "Checks if the value of the field is `CRYPTO0`"]
208    #[inline(always)]
209    pub fn is_crypto0(&self) -> bool {
210        *self == SOURCESEL_A::CRYPTO0
211    }
212    #[doc = "Checks if the value of the field is `CSEN`"]
213    #[inline(always)]
214    pub fn is_csen(&self) -> bool {
215        *self == SOURCESEL_A::CSEN
216    }
217    #[doc = "Checks if the value of the field is `LESENSE`"]
218    #[inline(always)]
219    pub fn is_lesense(&self) -> bool {
220        *self == SOURCESEL_A::LESENSE
221    }
222}
223#[doc = "Field `SOURCESEL` writer - Source Select"]
224pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH6_REQSEL_SPEC, u8, SOURCESEL_A, 6, 16>;
225impl<'a> SOURCESEL_W<'a> {
226    #[doc = "No source selected"]
227    #[inline(always)]
228    pub fn none(self) -> &'a mut W {
229        self.variant(SOURCESEL_A::NONE)
230    }
231    #[doc = "Peripheral Reflex System"]
232    #[inline(always)]
233    pub fn prs(self) -> &'a mut W {
234        self.variant(SOURCESEL_A::PRS)
235    }
236    #[doc = "Analog to Digital Converter 0"]
237    #[inline(always)]
238    pub fn adc0(self) -> &'a mut W {
239        self.variant(SOURCESEL_A::ADC0)
240    }
241    #[doc = "Digital to Analog Converter 0"]
242    #[inline(always)]
243    pub fn vdac0(self) -> &'a mut W {
244        self.variant(SOURCESEL_A::VDAC0)
245    }
246    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
247    #[inline(always)]
248    pub fn usart0(self) -> &'a mut W {
249        self.variant(SOURCESEL_A::USART0)
250    }
251    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
252    #[inline(always)]
253    pub fn usart1(self) -> &'a mut W {
254        self.variant(SOURCESEL_A::USART1)
255    }
256    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
257    #[inline(always)]
258    pub fn usart2(self) -> &'a mut W {
259        self.variant(SOURCESEL_A::USART2)
260    }
261    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
262    #[inline(always)]
263    pub fn usart3(self) -> &'a mut W {
264        self.variant(SOURCESEL_A::USART3)
265    }
266    #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
267    #[inline(always)]
268    pub fn uart0(self) -> &'a mut W {
269        self.variant(SOURCESEL_A::UART0)
270    }
271    #[doc = "Low Energy UART 0"]
272    #[inline(always)]
273    pub fn leuart0(self) -> &'a mut W {
274        self.variant(SOURCESEL_A::LEUART0)
275    }
276    #[doc = "I2C 0"]
277    #[inline(always)]
278    pub fn i2c0(self) -> &'a mut W {
279        self.variant(SOURCESEL_A::I2C0)
280    }
281    #[doc = "I2C 1"]
282    #[inline(always)]
283    pub fn i2c1(self) -> &'a mut W {
284        self.variant(SOURCESEL_A::I2C1)
285    }
286    #[doc = "Timer 0"]
287    #[inline(always)]
288    pub fn timer0(self) -> &'a mut W {
289        self.variant(SOURCESEL_A::TIMER0)
290    }
291    #[doc = "Timer 1"]
292    #[inline(always)]
293    pub fn timer1(self) -> &'a mut W {
294        self.variant(SOURCESEL_A::TIMER1)
295    }
296    #[doc = "Wide Timer 0"]
297    #[inline(always)]
298    pub fn wtimer0(self) -> &'a mut W {
299        self.variant(SOURCESEL_A::WTIMER0)
300    }
301    #[doc = "Wide Timer 1"]
302    #[inline(always)]
303    pub fn wtimer1(self) -> &'a mut W {
304        self.variant(SOURCESEL_A::WTIMER1)
305    }
306    #[doc = "Memory System Controller"]
307    #[inline(always)]
308    pub fn msc(self) -> &'a mut W {
309        self.variant(SOURCESEL_A::MSC)
310    }
311    #[doc = "Advanced Encryption Standard Accelerator"]
312    #[inline(always)]
313    pub fn crypto0(self) -> &'a mut W {
314        self.variant(SOURCESEL_A::CRYPTO0)
315    }
316    #[doc = "Capacitive touch sense module"]
317    #[inline(always)]
318    pub fn csen(self) -> &'a mut W {
319        self.variant(SOURCESEL_A::CSEN)
320    }
321    #[doc = "Low Energy Sensor Interface"]
322    #[inline(always)]
323    pub fn lesense(self) -> &'a mut W {
324        self.variant(SOURCESEL_A::LESENSE)
325    }
326}
327impl R {
328    #[doc = "Bits 0:3 - Signal Select"]
329    #[inline(always)]
330    pub fn sigsel(&self) -> SIGSEL_R {
331        SIGSEL_R::new((self.bits & 0x0f) as u8)
332    }
333    #[doc = "Bits 16:21 - Source Select"]
334    #[inline(always)]
335    pub fn sourcesel(&self) -> SOURCESEL_R {
336        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
337    }
338}
339impl W {
340    #[doc = "Bits 0:3 - Signal Select"]
341    #[inline(always)]
342    pub fn sigsel(&mut self) -> SIGSEL_W {
343        SIGSEL_W::new(self)
344    }
345    #[doc = "Bits 16:21 - Source Select"]
346    #[inline(always)]
347    pub fn sourcesel(&mut self) -> SOURCESEL_W {
348        SOURCESEL_W::new(self)
349    }
350    #[doc = "Writes raw bits to the register."]
351    #[inline(always)]
352    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
353        self.0.bits(bits);
354        self
355    }
356}
357#[doc = "Channel Peripheral Request Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch6_reqsel](index.html) module"]
358pub struct CH6_REQSEL_SPEC;
359impl crate::RegisterSpec for CH6_REQSEL_SPEC {
360    type Ux = u32;
361}
362#[doc = "`read()` method returns [ch6_reqsel::R](R) reader structure"]
363impl crate::Readable for CH6_REQSEL_SPEC {
364    type Reader = R;
365}
366#[doc = "`write(|w| ..)` method takes [ch6_reqsel::W](W) writer structure"]
367impl crate::Writable for CH6_REQSEL_SPEC {
368    type Writer = W;
369}
370#[doc = "`reset()` method sets CH6_REQSEL to value 0"]
371impl crate::Resettable for CH6_REQSEL_SPEC {
372    #[inline(always)]
373    fn reset_value() -> Self::Ux {
374        0
375    }
376}
efm32tg11b120_pac/ldma/ch6_reqsel.rs

efm32tg11b120_pac/ldma/
ch6_reqsel.rs
