efm32tg11b_pac/efm32tg11b540/smu/
ppupatd1.rs

1#[doc = "Register `PPUPATD1` reader"]
2pub struct R(crate::R<PPUPATD1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PPUPATD1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PPUPATD1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PPUPATD1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PPUPATD1` writer"]
17pub struct W(crate::W<PPUPATD1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PPUPATD1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PPUPATD1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PPUPATD1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `USART3` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
38pub type USART3_R = crate::BitReader<bool>;
39#[doc = "Field `USART3` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
40pub type USART3_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
41#[doc = "Field `WDOG0` reader - Watchdog access control bit"]
42pub type WDOG0_R = crate::BitReader<bool>;
43#[doc = "Field `WDOG0` writer - Watchdog access control bit"]
44pub type WDOG0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
45#[doc = "Field `WTIMER0` reader - Wide Timer 0 access control bit"]
46pub type WTIMER0_R = crate::BitReader<bool>;
47#[doc = "Field `WTIMER0` writer - Wide Timer 0 access control bit"]
48pub type WTIMER0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
49#[doc = "Field `WTIMER1` reader - Wide Timer 1 access control bit"]
50pub type WTIMER1_R = crate::BitReader<bool>;
51#[doc = "Field `WTIMER1` writer - Wide Timer 1 access control bit"]
52pub type WTIMER1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
53impl R {
54    #[doc = "Bit 0 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
55    #[inline(always)]
56    pub fn usart3(&self) -> USART3_R {
57        USART3_R::new((self.bits & 1) != 0)
58    }
59    #[doc = "Bit 1 - Watchdog access control bit"]
60    #[inline(always)]
61    pub fn wdog0(&self) -> WDOG0_R {
62        WDOG0_R::new(((self.bits >> 1) & 1) != 0)
63    }
64    #[doc = "Bit 2 - Wide Timer 0 access control bit"]
65    #[inline(always)]
66    pub fn wtimer0(&self) -> WTIMER0_R {
67        WTIMER0_R::new(((self.bits >> 2) & 1) != 0)
68    }
69    #[doc = "Bit 3 - Wide Timer 1 access control bit"]
70    #[inline(always)]
71    pub fn wtimer1(&self) -> WTIMER1_R {
72        WTIMER1_R::new(((self.bits >> 3) & 1) != 0)
73    }
74}
75impl W {
76    #[doc = "Bit 0 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
77    #[inline(always)]
78    #[must_use]
79    pub fn usart3(&mut self) -> USART3_W<0> {
80        USART3_W::new(self)
81    }
82    #[doc = "Bit 1 - Watchdog access control bit"]
83    #[inline(always)]
84    #[must_use]
85    pub fn wdog0(&mut self) -> WDOG0_W<1> {
86        WDOG0_W::new(self)
87    }
88    #[doc = "Bit 2 - Wide Timer 0 access control bit"]
89    #[inline(always)]
90    #[must_use]
91    pub fn wtimer0(&mut self) -> WTIMER0_W<2> {
92        WTIMER0_W::new(self)
93    }
94    #[doc = "Bit 3 - Wide Timer 1 access control bit"]
95    #[inline(always)]
96    #[must_use]
97    pub fn wtimer1(&mut self) -> WTIMER1_W<3> {
98        WTIMER1_W::new(self)
99    }
100    #[doc = "Writes raw bits to the register."]
101    #[inline(always)]
102    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
103        self.0.bits(bits);
104        self
105    }
106}
107#[doc = "PPU Privilege Access Type Descriptor 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ppupatd1](index.html) module"]
108pub struct PPUPATD1_SPEC;
109impl crate::RegisterSpec for PPUPATD1_SPEC {
110    type Ux = u32;
111}
112#[doc = "`read()` method returns [ppupatd1::R](R) reader structure"]
113impl crate::Readable for PPUPATD1_SPEC {
114    type Reader = R;
115}
116#[doc = "`write(|w| ..)` method takes [ppupatd1::W](W) writer structure"]
117impl crate::Writable for PPUPATD1_SPEC {
118    type Writer = W;
119    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
120    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
121}
122#[doc = "`reset()` method sets PPUPATD1 to value 0"]
123impl crate::Resettable for PPUPATD1_SPEC {
124    const RESET_VALUE: Self::Ux = 0;
125}
efm32tg11b_pac/efm32tg11b540/smu/ppupatd1.rs

efm32tg11b_pac/efm32tg11b540/smu/
ppupatd1.rs
