efm32tg11b_pac/efm32tg11b540/prs/
ch1_ctrl.rs

1#[doc = "Register `CH1_CTRL` reader"]
2pub struct R(crate::R<CH1_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH1_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH1_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH1_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH1_CTRL` writer"]
17pub struct W(crate::W<CH1_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH1_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH1_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH1_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CH1_CTRL_SPEC, u8, u8, 3, O>;
41#[doc = "Field `SOURCESEL` reader - Source Select"]
42pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
43#[doc = "Source Select\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45#[repr(u8)]
46pub enum SOURCESEL_A {
47    #[doc = "0: No source selected"]
48    NONE = 0,
49    #[doc = "1: Peripheral Reflex System"]
50    PRSL = 1,
51    #[doc = "2: Analog Comparator 0"]
52    ACMP0 = 2,
53    #[doc = "3: Analog Comparator 1"]
54    ACMP1 = 3,
55    #[doc = "4: Analog to Digital Converter 0"]
56    ADC0 = 4,
57    #[doc = "5: Real-Time Counter and Calendar"]
58    RTCC = 5,
59    #[doc = "6: General purpose Input/Output"]
60    GPIOL = 6,
61    #[doc = "7: General purpose Input/Output"]
62    GPIOH = 7,
63    #[doc = "8: Low Energy Timer 0"]
64    LETIMER0 = 8,
65    #[doc = "9: Pulse Counter 0"]
66    PCNT0 = 9,
67    #[doc = "10: CRYOTIMER"]
68    CRYOTIMER = 10,
69    #[doc = "11: Clock Management Unit"]
70    CMU = 11,
71    #[doc = "17: Digital to Analog Converter 0"]
72    VDAC0 = 17,
73    #[doc = "18: Low Energy Sensor Interface"]
74    LESENSEL = 18,
75    #[doc = "19: Low Energy Sensor Interface"]
76    LESENSEH = 19,
77    #[doc = "20: Low Energy Sensor Interface"]
78    LESENSED = 20,
79    #[doc = "21: Low Energy Sensor Interface"]
80    LESENSE = 21,
81    #[doc = "32: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
82    USART0 = 32,
83    #[doc = "33: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
84    USART1 = 33,
85    #[doc = "34: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
86    USART2 = 34,
87    #[doc = "35: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
88    USART3 = 35,
89    #[doc = "36: Universal Asynchronous Receiver/Transmitter 0"]
90    UART0 = 36,
91    #[doc = "37: Timer 0"]
92    TIMER0 = 37,
93    #[doc = "38: Timer 1"]
94    TIMER1 = 38,
95    #[doc = "39: Wide Timer 0"]
96    WTIMER0 = 39,
97    #[doc = "40: Wide Timer 1"]
98    WTIMER1 = 40,
99    #[doc = "41: `101001`"]
100    CM0P = 41,
101}
102impl From<SOURCESEL_A> for u8 {
103    #[inline(always)]
104    fn from(variant: SOURCESEL_A) -> Self {
105        variant as _
106    }
107}
108impl SOURCESEL_R {
109    #[doc = "Get enumerated values variant"]
110    #[inline(always)]
111    pub fn variant(&self) -> Option<SOURCESEL_A> {
112        match self.bits {
113            0 => Some(SOURCESEL_A::NONE),
114            1 => Some(SOURCESEL_A::PRSL),
115            2 => Some(SOURCESEL_A::ACMP0),
116            3 => Some(SOURCESEL_A::ACMP1),
117            4 => Some(SOURCESEL_A::ADC0),
118            5 => Some(SOURCESEL_A::RTCC),
119            6 => Some(SOURCESEL_A::GPIOL),
120            7 => Some(SOURCESEL_A::GPIOH),
121            8 => Some(SOURCESEL_A::LETIMER0),
122            9 => Some(SOURCESEL_A::PCNT0),
123            10 => Some(SOURCESEL_A::CRYOTIMER),
124            11 => Some(SOURCESEL_A::CMU),
125            17 => Some(SOURCESEL_A::VDAC0),
126            18 => Some(SOURCESEL_A::LESENSEL),
127            19 => Some(SOURCESEL_A::LESENSEH),
128            20 => Some(SOURCESEL_A::LESENSED),
129            21 => Some(SOURCESEL_A::LESENSE),
130            32 => Some(SOURCESEL_A::USART0),
131            33 => Some(SOURCESEL_A::USART1),
132            34 => Some(SOURCESEL_A::USART2),
133            35 => Some(SOURCESEL_A::USART3),
134            36 => Some(SOURCESEL_A::UART0),
135            37 => Some(SOURCESEL_A::TIMER0),
136            38 => Some(SOURCESEL_A::TIMER1),
137            39 => Some(SOURCESEL_A::WTIMER0),
138            40 => Some(SOURCESEL_A::WTIMER1),
139            41 => Some(SOURCESEL_A::CM0P),
140            _ => None,
141        }
142    }
143    #[doc = "Checks if the value of the field is `NONE`"]
144    #[inline(always)]
145    pub fn is_none(&self) -> bool {
146        *self == SOURCESEL_A::NONE
147    }
148    #[doc = "Checks if the value of the field is `PRSL`"]
149    #[inline(always)]
150    pub fn is_prsl(&self) -> bool {
151        *self == SOURCESEL_A::PRSL
152    }
153    #[doc = "Checks if the value of the field is `ACMP0`"]
154    #[inline(always)]
155    pub fn is_acmp0(&self) -> bool {
156        *self == SOURCESEL_A::ACMP0
157    }
158    #[doc = "Checks if the value of the field is `ACMP1`"]
159    #[inline(always)]
160    pub fn is_acmp1(&self) -> bool {
161        *self == SOURCESEL_A::ACMP1
162    }
163    #[doc = "Checks if the value of the field is `ADC0`"]
164    #[inline(always)]
165    pub fn is_adc0(&self) -> bool {
166        *self == SOURCESEL_A::ADC0
167    }
168    #[doc = "Checks if the value of the field is `RTCC`"]
169    #[inline(always)]
170    pub fn is_rtcc(&self) -> bool {
171        *self == SOURCESEL_A::RTCC
172    }
173    #[doc = "Checks if the value of the field is `GPIOL`"]
174    #[inline(always)]
175    pub fn is_gpiol(&self) -> bool {
176        *self == SOURCESEL_A::GPIOL
177    }
178    #[doc = "Checks if the value of the field is `GPIOH`"]
179    #[inline(always)]
180    pub fn is_gpioh(&self) -> bool {
181        *self == SOURCESEL_A::GPIOH
182    }
183    #[doc = "Checks if the value of the field is `LETIMER0`"]
184    #[inline(always)]
185    pub fn is_letimer0(&self) -> bool {
186        *self == SOURCESEL_A::LETIMER0
187    }
188    #[doc = "Checks if the value of the field is `PCNT0`"]
189    #[inline(always)]
190    pub fn is_pcnt0(&self) -> bool {
191        *self == SOURCESEL_A::PCNT0
192    }
193    #[doc = "Checks if the value of the field is `CRYOTIMER`"]
194    #[inline(always)]
195    pub fn is_cryotimer(&self) -> bool {
196        *self == SOURCESEL_A::CRYOTIMER
197    }
198    #[doc = "Checks if the value of the field is `CMU`"]
199    #[inline(always)]
200    pub fn is_cmu(&self) -> bool {
201        *self == SOURCESEL_A::CMU
202    }
203    #[doc = "Checks if the value of the field is `VDAC0`"]
204    #[inline(always)]
205    pub fn is_vdac0(&self) -> bool {
206        *self == SOURCESEL_A::VDAC0
207    }
208    #[doc = "Checks if the value of the field is `LESENSEL`"]
209    #[inline(always)]
210    pub fn is_lesensel(&self) -> bool {
211        *self == SOURCESEL_A::LESENSEL
212    }
213    #[doc = "Checks if the value of the field is `LESENSEH`"]
214    #[inline(always)]
215    pub fn is_lesenseh(&self) -> bool {
216        *self == SOURCESEL_A::LESENSEH
217    }
218    #[doc = "Checks if the value of the field is `LESENSED`"]
219    #[inline(always)]
220    pub fn is_lesensed(&self) -> bool {
221        *self == SOURCESEL_A::LESENSED
222    }
223    #[doc = "Checks if the value of the field is `LESENSE`"]
224    #[inline(always)]
225    pub fn is_lesense(&self) -> bool {
226        *self == SOURCESEL_A::LESENSE
227    }
228    #[doc = "Checks if the value of the field is `USART0`"]
229    #[inline(always)]
230    pub fn is_usart0(&self) -> bool {
231        *self == SOURCESEL_A::USART0
232    }
233    #[doc = "Checks if the value of the field is `USART1`"]
234    #[inline(always)]
235    pub fn is_usart1(&self) -> bool {
236        *self == SOURCESEL_A::USART1
237    }
238    #[doc = "Checks if the value of the field is `USART2`"]
239    #[inline(always)]
240    pub fn is_usart2(&self) -> bool {
241        *self == SOURCESEL_A::USART2
242    }
243    #[doc = "Checks if the value of the field is `USART3`"]
244    #[inline(always)]
245    pub fn is_usart3(&self) -> bool {
246        *self == SOURCESEL_A::USART3
247    }
248    #[doc = "Checks if the value of the field is `UART0`"]
249    #[inline(always)]
250    pub fn is_uart0(&self) -> bool {
251        *self == SOURCESEL_A::UART0
252    }
253    #[doc = "Checks if the value of the field is `TIMER0`"]
254    #[inline(always)]
255    pub fn is_timer0(&self) -> bool {
256        *self == SOURCESEL_A::TIMER0
257    }
258    #[doc = "Checks if the value of the field is `TIMER1`"]
259    #[inline(always)]
260    pub fn is_timer1(&self) -> bool {
261        *self == SOURCESEL_A::TIMER1
262    }
263    #[doc = "Checks if the value of the field is `WTIMER0`"]
264    #[inline(always)]
265    pub fn is_wtimer0(&self) -> bool {
266        *self == SOURCESEL_A::WTIMER0
267    }
268    #[doc = "Checks if the value of the field is `WTIMER1`"]
269    #[inline(always)]
270    pub fn is_wtimer1(&self) -> bool {
271        *self == SOURCESEL_A::WTIMER1
272    }
273    #[doc = "Checks if the value of the field is `CM0P`"]
274    #[inline(always)]
275    pub fn is_cm0p(&self) -> bool {
276        *self == SOURCESEL_A::CM0P
277    }
278}
279#[doc = "Field `SOURCESEL` writer - Source Select"]
280pub type SOURCESEL_W<'a, const O: u8> =
281    crate::FieldWriter<'a, u32, CH1_CTRL_SPEC, u8, SOURCESEL_A, 7, O>;
282impl<'a, const O: u8> SOURCESEL_W<'a, O> {
283    #[doc = "No source selected"]
284    #[inline(always)]
285    pub fn none(self) -> &'a mut W {
286        self.variant(SOURCESEL_A::NONE)
287    }
288    #[doc = "Peripheral Reflex System"]
289    #[inline(always)]
290    pub fn prsl(self) -> &'a mut W {
291        self.variant(SOURCESEL_A::PRSL)
292    }
293    #[doc = "Analog Comparator 0"]
294    #[inline(always)]
295    pub fn acmp0(self) -> &'a mut W {
296        self.variant(SOURCESEL_A::ACMP0)
297    }
298    #[doc = "Analog Comparator 1"]
299    #[inline(always)]
300    pub fn acmp1(self) -> &'a mut W {
301        self.variant(SOURCESEL_A::ACMP1)
302    }
303    #[doc = "Analog to Digital Converter 0"]
304    #[inline(always)]
305    pub fn adc0(self) -> &'a mut W {
306        self.variant(SOURCESEL_A::ADC0)
307    }
308    #[doc = "Real-Time Counter and Calendar"]
309    #[inline(always)]
310    pub fn rtcc(self) -> &'a mut W {
311        self.variant(SOURCESEL_A::RTCC)
312    }
313    #[doc = "General purpose Input/Output"]
314    #[inline(always)]
315    pub fn gpiol(self) -> &'a mut W {
316        self.variant(SOURCESEL_A::GPIOL)
317    }
318    #[doc = "General purpose Input/Output"]
319    #[inline(always)]
320    pub fn gpioh(self) -> &'a mut W {
321        self.variant(SOURCESEL_A::GPIOH)
322    }
323    #[doc = "Low Energy Timer 0"]
324    #[inline(always)]
325    pub fn letimer0(self) -> &'a mut W {
326        self.variant(SOURCESEL_A::LETIMER0)
327    }
328    #[doc = "Pulse Counter 0"]
329    #[inline(always)]
330    pub fn pcnt0(self) -> &'a mut W {
331        self.variant(SOURCESEL_A::PCNT0)
332    }
333    #[doc = "CRYOTIMER"]
334    #[inline(always)]
335    pub fn cryotimer(self) -> &'a mut W {
336        self.variant(SOURCESEL_A::CRYOTIMER)
337    }
338    #[doc = "Clock Management Unit"]
339    #[inline(always)]
340    pub fn cmu(self) -> &'a mut W {
341        self.variant(SOURCESEL_A::CMU)
342    }
343    #[doc = "Digital to Analog Converter 0"]
344    #[inline(always)]
345    pub fn vdac0(self) -> &'a mut W {
346        self.variant(SOURCESEL_A::VDAC0)
347    }
348    #[doc = "Low Energy Sensor Interface"]
349    #[inline(always)]
350    pub fn lesensel(self) -> &'a mut W {
351        self.variant(SOURCESEL_A::LESENSEL)
352    }
353    #[doc = "Low Energy Sensor Interface"]
354    #[inline(always)]
355    pub fn lesenseh(self) -> &'a mut W {
356        self.variant(SOURCESEL_A::LESENSEH)
357    }
358    #[doc = "Low Energy Sensor Interface"]
359    #[inline(always)]
360    pub fn lesensed(self) -> &'a mut W {
361        self.variant(SOURCESEL_A::LESENSED)
362    }
363    #[doc = "Low Energy Sensor Interface"]
364    #[inline(always)]
365    pub fn lesense(self) -> &'a mut W {
366        self.variant(SOURCESEL_A::LESENSE)
367    }
368    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
369    #[inline(always)]
370    pub fn usart0(self) -> &'a mut W {
371        self.variant(SOURCESEL_A::USART0)
372    }
373    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
374    #[inline(always)]
375    pub fn usart1(self) -> &'a mut W {
376        self.variant(SOURCESEL_A::USART1)
377    }
378    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
379    #[inline(always)]
380    pub fn usart2(self) -> &'a mut W {
381        self.variant(SOURCESEL_A::USART2)
382    }
383    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
384    #[inline(always)]
385    pub fn usart3(self) -> &'a mut W {
386        self.variant(SOURCESEL_A::USART3)
387    }
388    #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
389    #[inline(always)]
390    pub fn uart0(self) -> &'a mut W {
391        self.variant(SOURCESEL_A::UART0)
392    }
393    #[doc = "Timer 0"]
394    #[inline(always)]
395    pub fn timer0(self) -> &'a mut W {
396        self.variant(SOURCESEL_A::TIMER0)
397    }
398    #[doc = "Timer 1"]
399    #[inline(always)]
400    pub fn timer1(self) -> &'a mut W {
401        self.variant(SOURCESEL_A::TIMER1)
402    }
403    #[doc = "Wide Timer 0"]
404    #[inline(always)]
405    pub fn wtimer0(self) -> &'a mut W {
406        self.variant(SOURCESEL_A::WTIMER0)
407    }
408    #[doc = "Wide Timer 1"]
409    #[inline(always)]
410    pub fn wtimer1(self) -> &'a mut W {
411        self.variant(SOURCESEL_A::WTIMER1)
412    }
413    #[doc = "`101001`"]
414    #[inline(always)]
415    pub fn cm0p(self) -> &'a mut W {
416        self.variant(SOURCESEL_A::CM0P)
417    }
418}
419#[doc = "Field `EDSEL` reader - Edge Detect Select"]
420pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
421#[doc = "Edge Detect Select\n\nValue on reset: 0"]
422#[derive(Clone, Copy, Debug, PartialEq, Eq)]
423#[repr(u8)]
424pub enum EDSEL_A {
425    #[doc = "0: Signal is left as it is"]
426    OFF = 0,
427    #[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
428    POSEDGE = 1,
429    #[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
430    NEGEDGE = 2,
431    #[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
432    BOTHEDGES = 3,
433}
434impl From<EDSEL_A> for u8 {
435    #[inline(always)]
436    fn from(variant: EDSEL_A) -> Self {
437        variant as _
438    }
439}
440impl EDSEL_R {
441    #[doc = "Get enumerated values variant"]
442    #[inline(always)]
443    pub fn variant(&self) -> EDSEL_A {
444        match self.bits {
445            0 => EDSEL_A::OFF,
446            1 => EDSEL_A::POSEDGE,
447            2 => EDSEL_A::NEGEDGE,
448            3 => EDSEL_A::BOTHEDGES,
449            _ => unreachable!(),
450        }
451    }
452    #[doc = "Checks if the value of the field is `OFF`"]
453    #[inline(always)]
454    pub fn is_off(&self) -> bool {
455        *self == EDSEL_A::OFF
456    }
457    #[doc = "Checks if the value of the field is `POSEDGE`"]
458    #[inline(always)]
459    pub fn is_posedge(&self) -> bool {
460        *self == EDSEL_A::POSEDGE
461    }
462    #[doc = "Checks if the value of the field is `NEGEDGE`"]
463    #[inline(always)]
464    pub fn is_negedge(&self) -> bool {
465        *self == EDSEL_A::NEGEDGE
466    }
467    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
468    #[inline(always)]
469    pub fn is_bothedges(&self) -> bool {
470        *self == EDSEL_A::BOTHEDGES
471    }
472}
473#[doc = "Field `EDSEL` writer - Edge Detect Select"]
474pub type EDSEL_W<'a, const O: u8> =
475    crate::FieldWriterSafe<'a, u32, CH1_CTRL_SPEC, u8, EDSEL_A, 2, O>;
476impl<'a, const O: u8> EDSEL_W<'a, O> {
477    #[doc = "Signal is left as it is"]
478    #[inline(always)]
479    pub fn off(self) -> &'a mut W {
480        self.variant(EDSEL_A::OFF)
481    }
482    #[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
483    #[inline(always)]
484    pub fn posedge(self) -> &'a mut W {
485        self.variant(EDSEL_A::POSEDGE)
486    }
487    #[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
488    #[inline(always)]
489    pub fn negedge(self) -> &'a mut W {
490        self.variant(EDSEL_A::NEGEDGE)
491    }
492    #[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
493    #[inline(always)]
494    pub fn bothedges(self) -> &'a mut W {
495        self.variant(EDSEL_A::BOTHEDGES)
496    }
497}
498#[doc = "Field `STRETCH` reader - Stretch Channel Output"]
499pub type STRETCH_R = crate::BitReader<bool>;
500#[doc = "Field `STRETCH` writer - Stretch Channel Output"]
501pub type STRETCH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH1_CTRL_SPEC, bool, O>;
502#[doc = "Field `INV` reader - Invert Channel"]
503pub type INV_R = crate::BitReader<bool>;
504#[doc = "Field `INV` writer - Invert Channel"]
505pub type INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH1_CTRL_SPEC, bool, O>;
506#[doc = "Field `ORPREV` reader - Or Previous"]
507pub type ORPREV_R = crate::BitReader<bool>;
508#[doc = "Field `ORPREV` writer - Or Previous"]
509pub type ORPREV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH1_CTRL_SPEC, bool, O>;
510#[doc = "Field `ANDNEXT` reader - And Next"]
511pub type ANDNEXT_R = crate::BitReader<bool>;
512#[doc = "Field `ANDNEXT` writer - And Next"]
513pub type ANDNEXT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH1_CTRL_SPEC, bool, O>;
514#[doc = "Field `ASYNC` reader - Asynchronous Reflex"]
515pub type ASYNC_R = crate::BitReader<bool>;
516#[doc = "Field `ASYNC` writer - Asynchronous Reflex"]
517pub type ASYNC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH1_CTRL_SPEC, bool, O>;
518impl R {
519    #[doc = "Bits 0:2 - Signal Select"]
520    #[inline(always)]
521    pub fn sigsel(&self) -> SIGSEL_R {
522        SIGSEL_R::new((self.bits & 7) as u8)
523    }
524    #[doc = "Bits 8:14 - Source Select"]
525    #[inline(always)]
526    pub fn sourcesel(&self) -> SOURCESEL_R {
527        SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
528    }
529    #[doc = "Bits 20:21 - Edge Detect Select"]
530    #[inline(always)]
531    pub fn edsel(&self) -> EDSEL_R {
532        EDSEL_R::new(((self.bits >> 20) & 3) as u8)
533    }
534    #[doc = "Bit 25 - Stretch Channel Output"]
535    #[inline(always)]
536    pub fn stretch(&self) -> STRETCH_R {
537        STRETCH_R::new(((self.bits >> 25) & 1) != 0)
538    }
539    #[doc = "Bit 26 - Invert Channel"]
540    #[inline(always)]
541    pub fn inv(&self) -> INV_R {
542        INV_R::new(((self.bits >> 26) & 1) != 0)
543    }
544    #[doc = "Bit 27 - Or Previous"]
545    #[inline(always)]
546    pub fn orprev(&self) -> ORPREV_R {
547        ORPREV_R::new(((self.bits >> 27) & 1) != 0)
548    }
549    #[doc = "Bit 28 - And Next"]
550    #[inline(always)]
551    pub fn andnext(&self) -> ANDNEXT_R {
552        ANDNEXT_R::new(((self.bits >> 28) & 1) != 0)
553    }
554    #[doc = "Bit 30 - Asynchronous Reflex"]
555    #[inline(always)]
556    pub fn async_(&self) -> ASYNC_R {
557        ASYNC_R::new(((self.bits >> 30) & 1) != 0)
558    }
559}
560impl W {
561    #[doc = "Bits 0:2 - Signal Select"]
562    #[inline(always)]
563    #[must_use]
564    pub fn sigsel(&mut self) -> SIGSEL_W<0> {
565        SIGSEL_W::new(self)
566    }
567    #[doc = "Bits 8:14 - Source Select"]
568    #[inline(always)]
569    #[must_use]
570    pub fn sourcesel(&mut self) -> SOURCESEL_W<8> {
571        SOURCESEL_W::new(self)
572    }
573    #[doc = "Bits 20:21 - Edge Detect Select"]
574    #[inline(always)]
575    #[must_use]
576    pub fn edsel(&mut self) -> EDSEL_W<20> {
577        EDSEL_W::new(self)
578    }
579    #[doc = "Bit 25 - Stretch Channel Output"]
580    #[inline(always)]
581    #[must_use]
582    pub fn stretch(&mut self) -> STRETCH_W<25> {
583        STRETCH_W::new(self)
584    }
585    #[doc = "Bit 26 - Invert Channel"]
586    #[inline(always)]
587    #[must_use]
588    pub fn inv(&mut self) -> INV_W<26> {
589        INV_W::new(self)
590    }
591    #[doc = "Bit 27 - Or Previous"]
592    #[inline(always)]
593    #[must_use]
594    pub fn orprev(&mut self) -> ORPREV_W<27> {
595        ORPREV_W::new(self)
596    }
597    #[doc = "Bit 28 - And Next"]
598    #[inline(always)]
599    #[must_use]
600    pub fn andnext(&mut self) -> ANDNEXT_W<28> {
601        ANDNEXT_W::new(self)
602    }
603    #[doc = "Bit 30 - Asynchronous Reflex"]
604    #[inline(always)]
605    #[must_use]
606    pub fn async_(&mut self) -> ASYNC_W<30> {
607        ASYNC_W::new(self)
608    }
609    #[doc = "Writes raw bits to the register."]
610    #[inline(always)]
611    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
612        self.0.bits(bits);
613        self
614    }
615}
616#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch1_ctrl](index.html) module"]
617pub struct CH1_CTRL_SPEC;
618impl crate::RegisterSpec for CH1_CTRL_SPEC {
619    type Ux = u32;
620}
621#[doc = "`read()` method returns [ch1_ctrl::R](R) reader structure"]
622impl crate::Readable for CH1_CTRL_SPEC {
623    type Reader = R;
624}
625#[doc = "`write(|w| ..)` method takes [ch1_ctrl::W](W) writer structure"]
626impl crate::Writable for CH1_CTRL_SPEC {
627    type Writer = W;
628    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
629    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
630}
631#[doc = "`reset()` method sets CH1_CTRL to value 0"]
632impl crate::Resettable for CH1_CTRL_SPEC {
633    const RESET_VALUE: Self::Ux = 0;
634}
efm32tg11b_pac/efm32tg11b540/prs/ch1_ctrl.rs

efm32tg11b_pac/efm32tg11b540/prs/
ch1_ctrl.rs
