efm32tg11b_pac/efm32tg11b540/ldma/
ch2_reqsel.rs

1#[doc = "Register `CH2_REQSEL` reader"]
2pub struct R(crate::R<CH2_REQSEL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH2_REQSEL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH2_REQSEL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH2_REQSEL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH2_REQSEL` writer"]
17pub struct W(crate::W<CH2_REQSEL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH2_REQSEL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH2_REQSEL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH2_REQSEL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CH2_REQSEL_SPEC, u8, u8, 4, O>;
41#[doc = "Field `SOURCESEL` reader - Source Select"]
42pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
43#[doc = "Source Select\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45#[repr(u8)]
46pub enum SOURCESEL_A {
47    #[doc = "0: No source selected"]
48    NONE = 0,
49    #[doc = "1: Peripheral Reflex System"]
50    PRS = 1,
51    #[doc = "8: Analog to Digital Converter 0"]
52    ADC0 = 8,
53    #[doc = "10: Digital to Analog Converter 0"]
54    VDAC0 = 10,
55    #[doc = "12: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
56    USART0 = 12,
57    #[doc = "13: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
58    USART1 = 13,
59    #[doc = "14: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
60    USART2 = 14,
61    #[doc = "15: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
62    USART3 = 15,
63    #[doc = "18: Universal Asynchronous Receiver/Transmitter 0"]
64    UART0 = 18,
65    #[doc = "20: Low Energy UART 0"]
66    LEUART0 = 20,
67    #[doc = "22: I2C 0"]
68    I2C0 = 22,
69    #[doc = "23: I2C 1"]
70    I2C1 = 23,
71    #[doc = "25: Timer 0"]
72    TIMER0 = 25,
73    #[doc = "26: Timer 1"]
74    TIMER1 = 26,
75    #[doc = "32: Wide Timer 0"]
76    WTIMER0 = 32,
77    #[doc = "33: Wide Timer 1"]
78    WTIMER1 = 33,
79    #[doc = "48: Memory System Controller"]
80    MSC = 48,
81    #[doc = "49: Advanced Encryption Standard Accelerator"]
82    CRYPTO0 = 49,
83    #[doc = "61: Capacitive touch sense module"]
84    CSEN = 61,
85    #[doc = "62: Low Energy Sensor Interface"]
86    LESENSE = 62,
87}
88impl From<SOURCESEL_A> for u8 {
89    #[inline(always)]
90    fn from(variant: SOURCESEL_A) -> Self {
91        variant as _
92    }
93}
94impl SOURCESEL_R {
95    #[doc = "Get enumerated values variant"]
96    #[inline(always)]
97    pub fn variant(&self) -> Option<SOURCESEL_A> {
98        match self.bits {
99            0 => Some(SOURCESEL_A::NONE),
100            1 => Some(SOURCESEL_A::PRS),
101            8 => Some(SOURCESEL_A::ADC0),
102            10 => Some(SOURCESEL_A::VDAC0),
103            12 => Some(SOURCESEL_A::USART0),
104            13 => Some(SOURCESEL_A::USART1),
105            14 => Some(SOURCESEL_A::USART2),
106            15 => Some(SOURCESEL_A::USART3),
107            18 => Some(SOURCESEL_A::UART0),
108            20 => Some(SOURCESEL_A::LEUART0),
109            22 => Some(SOURCESEL_A::I2C0),
110            23 => Some(SOURCESEL_A::I2C1),
111            25 => Some(SOURCESEL_A::TIMER0),
112            26 => Some(SOURCESEL_A::TIMER1),
113            32 => Some(SOURCESEL_A::WTIMER0),
114            33 => Some(SOURCESEL_A::WTIMER1),
115            48 => Some(SOURCESEL_A::MSC),
116            49 => Some(SOURCESEL_A::CRYPTO0),
117            61 => Some(SOURCESEL_A::CSEN),
118            62 => Some(SOURCESEL_A::LESENSE),
119            _ => None,
120        }
121    }
122    #[doc = "Checks if the value of the field is `NONE`"]
123    #[inline(always)]
124    pub fn is_none(&self) -> bool {
125        *self == SOURCESEL_A::NONE
126    }
127    #[doc = "Checks if the value of the field is `PRS`"]
128    #[inline(always)]
129    pub fn is_prs(&self) -> bool {
130        *self == SOURCESEL_A::PRS
131    }
132    #[doc = "Checks if the value of the field is `ADC0`"]
133    #[inline(always)]
134    pub fn is_adc0(&self) -> bool {
135        *self == SOURCESEL_A::ADC0
136    }
137    #[doc = "Checks if the value of the field is `VDAC0`"]
138    #[inline(always)]
139    pub fn is_vdac0(&self) -> bool {
140        *self == SOURCESEL_A::VDAC0
141    }
142    #[doc = "Checks if the value of the field is `USART0`"]
143    #[inline(always)]
144    pub fn is_usart0(&self) -> bool {
145        *self == SOURCESEL_A::USART0
146    }
147    #[doc = "Checks if the value of the field is `USART1`"]
148    #[inline(always)]
149    pub fn is_usart1(&self) -> bool {
150        *self == SOURCESEL_A::USART1
151    }
152    #[doc = "Checks if the value of the field is `USART2`"]
153    #[inline(always)]
154    pub fn is_usart2(&self) -> bool {
155        *self == SOURCESEL_A::USART2
156    }
157    #[doc = "Checks if the value of the field is `USART3`"]
158    #[inline(always)]
159    pub fn is_usart3(&self) -> bool {
160        *self == SOURCESEL_A::USART3
161    }
162    #[doc = "Checks if the value of the field is `UART0`"]
163    #[inline(always)]
164    pub fn is_uart0(&self) -> bool {
165        *self == SOURCESEL_A::UART0
166    }
167    #[doc = "Checks if the value of the field is `LEUART0`"]
168    #[inline(always)]
169    pub fn is_leuart0(&self) -> bool {
170        *self == SOURCESEL_A::LEUART0
171    }
172    #[doc = "Checks if the value of the field is `I2C0`"]
173    #[inline(always)]
174    pub fn is_i2c0(&self) -> bool {
175        *self == SOURCESEL_A::I2C0
176    }
177    #[doc = "Checks if the value of the field is `I2C1`"]
178    #[inline(always)]
179    pub fn is_i2c1(&self) -> bool {
180        *self == SOURCESEL_A::I2C1
181    }
182    #[doc = "Checks if the value of the field is `TIMER0`"]
183    #[inline(always)]
184    pub fn is_timer0(&self) -> bool {
185        *self == SOURCESEL_A::TIMER0
186    }
187    #[doc = "Checks if the value of the field is `TIMER1`"]
188    #[inline(always)]
189    pub fn is_timer1(&self) -> bool {
190        *self == SOURCESEL_A::TIMER1
191    }
192    #[doc = "Checks if the value of the field is `WTIMER0`"]
193    #[inline(always)]
194    pub fn is_wtimer0(&self) -> bool {
195        *self == SOURCESEL_A::WTIMER0
196    }
197    #[doc = "Checks if the value of the field is `WTIMER1`"]
198    #[inline(always)]
199    pub fn is_wtimer1(&self) -> bool {
200        *self == SOURCESEL_A::WTIMER1
201    }
202    #[doc = "Checks if the value of the field is `MSC`"]
203    #[inline(always)]
204    pub fn is_msc(&self) -> bool {
205        *self == SOURCESEL_A::MSC
206    }
207    #[doc = "Checks if the value of the field is `CRYPTO0`"]
208    #[inline(always)]
209    pub fn is_crypto0(&self) -> bool {
210        *self == SOURCESEL_A::CRYPTO0
211    }
212    #[doc = "Checks if the value of the field is `CSEN`"]
213    #[inline(always)]
214    pub fn is_csen(&self) -> bool {
215        *self == SOURCESEL_A::CSEN
216    }
217    #[doc = "Checks if the value of the field is `LESENSE`"]
218    #[inline(always)]
219    pub fn is_lesense(&self) -> bool {
220        *self == SOURCESEL_A::LESENSE
221    }
222}
223#[doc = "Field `SOURCESEL` writer - Source Select"]
224pub type SOURCESEL_W<'a, const O: u8> =
225    crate::FieldWriter<'a, u32, CH2_REQSEL_SPEC, u8, SOURCESEL_A, 6, O>;
226impl<'a, const O: u8> SOURCESEL_W<'a, O> {
227    #[doc = "No source selected"]
228    #[inline(always)]
229    pub fn none(self) -> &'a mut W {
230        self.variant(SOURCESEL_A::NONE)
231    }
232    #[doc = "Peripheral Reflex System"]
233    #[inline(always)]
234    pub fn prs(self) -> &'a mut W {
235        self.variant(SOURCESEL_A::PRS)
236    }
237    #[doc = "Analog to Digital Converter 0"]
238    #[inline(always)]
239    pub fn adc0(self) -> &'a mut W {
240        self.variant(SOURCESEL_A::ADC0)
241    }
242    #[doc = "Digital to Analog Converter 0"]
243    #[inline(always)]
244    pub fn vdac0(self) -> &'a mut W {
245        self.variant(SOURCESEL_A::VDAC0)
246    }
247    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
248    #[inline(always)]
249    pub fn usart0(self) -> &'a mut W {
250        self.variant(SOURCESEL_A::USART0)
251    }
252    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
253    #[inline(always)]
254    pub fn usart1(self) -> &'a mut W {
255        self.variant(SOURCESEL_A::USART1)
256    }
257    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
258    #[inline(always)]
259    pub fn usart2(self) -> &'a mut W {
260        self.variant(SOURCESEL_A::USART2)
261    }
262    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
263    #[inline(always)]
264    pub fn usart3(self) -> &'a mut W {
265        self.variant(SOURCESEL_A::USART3)
266    }
267    #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
268    #[inline(always)]
269    pub fn uart0(self) -> &'a mut W {
270        self.variant(SOURCESEL_A::UART0)
271    }
272    #[doc = "Low Energy UART 0"]
273    #[inline(always)]
274    pub fn leuart0(self) -> &'a mut W {
275        self.variant(SOURCESEL_A::LEUART0)
276    }
277    #[doc = "I2C 0"]
278    #[inline(always)]
279    pub fn i2c0(self) -> &'a mut W {
280        self.variant(SOURCESEL_A::I2C0)
281    }
282    #[doc = "I2C 1"]
283    #[inline(always)]
284    pub fn i2c1(self) -> &'a mut W {
285        self.variant(SOURCESEL_A::I2C1)
286    }
287    #[doc = "Timer 0"]
288    #[inline(always)]
289    pub fn timer0(self) -> &'a mut W {
290        self.variant(SOURCESEL_A::TIMER0)
291    }
292    #[doc = "Timer 1"]
293    #[inline(always)]
294    pub fn timer1(self) -> &'a mut W {
295        self.variant(SOURCESEL_A::TIMER1)
296    }
297    #[doc = "Wide Timer 0"]
298    #[inline(always)]
299    pub fn wtimer0(self) -> &'a mut W {
300        self.variant(SOURCESEL_A::WTIMER0)
301    }
302    #[doc = "Wide Timer 1"]
303    #[inline(always)]
304    pub fn wtimer1(self) -> &'a mut W {
305        self.variant(SOURCESEL_A::WTIMER1)
306    }
307    #[doc = "Memory System Controller"]
308    #[inline(always)]
309    pub fn msc(self) -> &'a mut W {
310        self.variant(SOURCESEL_A::MSC)
311    }
312    #[doc = "Advanced Encryption Standard Accelerator"]
313    #[inline(always)]
314    pub fn crypto0(self) -> &'a mut W {
315        self.variant(SOURCESEL_A::CRYPTO0)
316    }
317    #[doc = "Capacitive touch sense module"]
318    #[inline(always)]
319    pub fn csen(self) -> &'a mut W {
320        self.variant(SOURCESEL_A::CSEN)
321    }
322    #[doc = "Low Energy Sensor Interface"]
323    #[inline(always)]
324    pub fn lesense(self) -> &'a mut W {
325        self.variant(SOURCESEL_A::LESENSE)
326    }
327}
328impl R {
329    #[doc = "Bits 0:3 - Signal Select"]
330    #[inline(always)]
331    pub fn sigsel(&self) -> SIGSEL_R {
332        SIGSEL_R::new((self.bits & 0x0f) as u8)
333    }
334    #[doc = "Bits 16:21 - Source Select"]
335    #[inline(always)]
336    pub fn sourcesel(&self) -> SOURCESEL_R {
337        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
338    }
339}
340impl W {
341    #[doc = "Bits 0:3 - Signal Select"]
342    #[inline(always)]
343    #[must_use]
344    pub fn sigsel(&mut self) -> SIGSEL_W<0> {
345        SIGSEL_W::new(self)
346    }
347    #[doc = "Bits 16:21 - Source Select"]
348    #[inline(always)]
349    #[must_use]
350    pub fn sourcesel(&mut self) -> SOURCESEL_W<16> {
351        SOURCESEL_W::new(self)
352    }
353    #[doc = "Writes raw bits to the register."]
354    #[inline(always)]
355    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
356        self.0.bits(bits);
357        self
358    }
359}
360#[doc = "Channel Peripheral Request Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch2_reqsel](index.html) module"]
361pub struct CH2_REQSEL_SPEC;
362impl crate::RegisterSpec for CH2_REQSEL_SPEC {
363    type Ux = u32;
364}
365#[doc = "`read()` method returns [ch2_reqsel::R](R) reader structure"]
366impl crate::Readable for CH2_REQSEL_SPEC {
367    type Reader = R;
368}
369#[doc = "`write(|w| ..)` method takes [ch2_reqsel::W](W) writer structure"]
370impl crate::Writable for CH2_REQSEL_SPEC {
371    type Writer = W;
372    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
373    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
374}
375#[doc = "`reset()` method sets CH2_REQSEL to value 0"]
376impl crate::Resettable for CH2_REQSEL_SPEC {
377    const RESET_VALUE: Self::Ux = 0;
378}
efm32tg11b_pac/efm32tg11b540/ldma/ch2_reqsel.rs

efm32tg11b_pac/efm32tg11b540/ldma/
ch2_reqsel.rs
