efm32tg11b_pac/efm32tg11b540/cmu/
hfxosteadystatectrl.rs

1#[doc = "Register `HFXOSTEADYSTATECTRL` reader"]
2pub struct R(crate::R<HFXOSTEADYSTATECTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HFXOSTEADYSTATECTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HFXOSTEADYSTATECTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HFXOSTEADYSTATECTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HFXOSTEADYSTATECTRL` writer"]
17pub struct W(crate::W<HFXOSTEADYSTATECTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HFXOSTEADYSTATECTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HFXOSTEADYSTATECTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HFXOSTEADYSTATECTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `IBTRIMXOCORE` reader - Sets the Steady State Oscillator Core Bias Current."]
38pub type IBTRIMXOCORE_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `IBTRIMXOCORE` writer - Sets the Steady State Oscillator Core Bias Current."]
40pub type IBTRIMXOCORE_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, HFXOSTEADYSTATECTRL_SPEC, u16, u16, 11, O>;
42#[doc = "Field `CTUNE` reader - Sets Oscillator Tuning Capacitance"]
43pub type CTUNE_R = crate::FieldReader<u16, u16>;
44#[doc = "Field `CTUNE` writer - Sets Oscillator Tuning Capacitance"]
45pub type CTUNE_W<'a, const O: u8> =
46    crate::FieldWriter<'a, u32, HFXOSTEADYSTATECTRL_SPEC, u16, u16, 9, O>;
47#[doc = "Field `PEAKDETEN` reader - Enables Oscillator Peak Detectors"]
48pub type PEAKDETEN_R = crate::BitReader<bool>;
49#[doc = "Field `PEAKDETEN` writer - Enables Oscillator Peak Detectors"]
50pub type PEAKDETEN_W<'a, const O: u8> =
51    crate::BitWriter<'a, u32, HFXOSTEADYSTATECTRL_SPEC, bool, O>;
52#[doc = "Field `PEAKMONEN` reader - Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO"]
53pub type PEAKMONEN_R = crate::BitReader<bool>;
54#[doc = "Field `PEAKMONEN` writer - Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO"]
55pub type PEAKMONEN_W<'a, const O: u8> =
56    crate::BitWriter<'a, u32, HFXOSTEADYSTATECTRL_SPEC, bool, O>;
57impl R {
58    #[doc = "Bits 0:10 - Sets the Steady State Oscillator Core Bias Current."]
59    #[inline(always)]
60    pub fn ibtrimxocore(&self) -> IBTRIMXOCORE_R {
61        IBTRIMXOCORE_R::new((self.bits & 0x07ff) as u16)
62    }
63    #[doc = "Bits 11:19 - Sets Oscillator Tuning Capacitance"]
64    #[inline(always)]
65    pub fn ctune(&self) -> CTUNE_R {
66        CTUNE_R::new(((self.bits >> 11) & 0x01ff) as u16)
67    }
68    #[doc = "Bit 26 - Enables Oscillator Peak Detectors"]
69    #[inline(always)]
70    pub fn peakdeten(&self) -> PEAKDETEN_R {
71        PEAKDETEN_R::new(((self.bits >> 26) & 1) != 0)
72    }
73    #[doc = "Bit 27 - Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO"]
74    #[inline(always)]
75    pub fn peakmonen(&self) -> PEAKMONEN_R {
76        PEAKMONEN_R::new(((self.bits >> 27) & 1) != 0)
77    }
78}
79impl W {
80    #[doc = "Bits 0:10 - Sets the Steady State Oscillator Core Bias Current."]
81    #[inline(always)]
82    #[must_use]
83    pub fn ibtrimxocore(&mut self) -> IBTRIMXOCORE_W<0> {
84        IBTRIMXOCORE_W::new(self)
85    }
86    #[doc = "Bits 11:19 - Sets Oscillator Tuning Capacitance"]
87    #[inline(always)]
88    #[must_use]
89    pub fn ctune(&mut self) -> CTUNE_W<11> {
90        CTUNE_W::new(self)
91    }
92    #[doc = "Bit 26 - Enables Oscillator Peak Detectors"]
93    #[inline(always)]
94    #[must_use]
95    pub fn peakdeten(&mut self) -> PEAKDETEN_W<26> {
96        PEAKDETEN_W::new(self)
97    }
98    #[doc = "Bit 27 - Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO"]
99    #[inline(always)]
100    #[must_use]
101    pub fn peakmonen(&mut self) -> PEAKMONEN_W<27> {
102        PEAKMONEN_W::new(self)
103    }
104    #[doc = "Writes raw bits to the register."]
105    #[inline(always)]
106    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
107        self.0.bits(bits);
108        self
109    }
110}
111#[doc = "HFXO Steady State Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfxosteadystatectrl](index.html) module"]
112pub struct HFXOSTEADYSTATECTRL_SPEC;
113impl crate::RegisterSpec for HFXOSTEADYSTATECTRL_SPEC {
114    type Ux = u32;
115}
116#[doc = "`read()` method returns [hfxosteadystatectrl::R](R) reader structure"]
117impl crate::Readable for HFXOSTEADYSTATECTRL_SPEC {
118    type Reader = R;
119}
120#[doc = "`write(|w| ..)` method takes [hfxosteadystatectrl::W](W) writer structure"]
121impl crate::Writable for HFXOSTEADYSTATECTRL_SPEC {
122    type Writer = W;
123    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
124    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
125}
126#[doc = "`reset()` method sets HFXOSTEADYSTATECTRL to value 0x0800_0100"]
127impl crate::Resettable for HFXOSTEADYSTATECTRL_SPEC {
128    const RESET_VALUE: Self::Ux = 0x0800_0100;
129}
efm32tg11b_pac/efm32tg11b540/cmu/hfxosteadystatectrl.rs

efm32tg11b_pac/efm32tg11b540/cmu/
hfxosteadystatectrl.rs
