efm32tg11b_pac/efm32tg11b540/can0/
ctrl.rs1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `INIT` reader - Initialize"]
38pub type INIT_R = crate::BitReader<bool>;
39#[doc = "Field `INIT` writer - Initialize"]
40pub type INIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
41#[doc = "Field `IE` reader - Module Interrupt Enable"]
42pub type IE_R = crate::BitReader<bool>;
43#[doc = "Field `IE` writer - Module Interrupt Enable"]
44pub type IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
45#[doc = "Field `SIE` reader - Status Change Interrupt Enable"]
46pub type SIE_R = crate::BitReader<bool>;
47#[doc = "Field `SIE` writer - Status Change Interrupt Enable"]
48pub type SIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
49#[doc = "Field `EIE` reader - Error Interrupt Enable"]
50pub type EIE_R = crate::BitReader<bool>;
51#[doc = "Field `EIE` writer - Error Interrupt Enable"]
52pub type EIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
53#[doc = "Field `DAR` reader - Disable Automatic Retransmission"]
54pub type DAR_R = crate::BitReader<bool>;
55#[doc = "Field `DAR` writer - Disable Automatic Retransmission"]
56pub type DAR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
57#[doc = "Field `CCE` reader - Configuration Change Enable"]
58pub type CCE_R = crate::BitReader<bool>;
59#[doc = "Field `CCE` writer - Configuration Change Enable"]
60pub type CCE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
61#[doc = "Field `TEST` reader - Test Mode Enable Write"]
62pub type TEST_R = crate::BitReader<bool>;
63#[doc = "Field `TEST` writer - Test Mode Enable Write"]
64pub type TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
65impl R {
66 #[doc = "Bit 0 - Initialize"]
67 #[inline(always)]
68 pub fn init(&self) -> INIT_R {
69 INIT_R::new((self.bits & 1) != 0)
70 }
71 #[doc = "Bit 1 - Module Interrupt Enable"]
72 #[inline(always)]
73 pub fn ie(&self) -> IE_R {
74 IE_R::new(((self.bits >> 1) & 1) != 0)
75 }
76 #[doc = "Bit 2 - Status Change Interrupt Enable"]
77 #[inline(always)]
78 pub fn sie(&self) -> SIE_R {
79 SIE_R::new(((self.bits >> 2) & 1) != 0)
80 }
81 #[doc = "Bit 3 - Error Interrupt Enable"]
82 #[inline(always)]
83 pub fn eie(&self) -> EIE_R {
84 EIE_R::new(((self.bits >> 3) & 1) != 0)
85 }
86 #[doc = "Bit 5 - Disable Automatic Retransmission"]
87 #[inline(always)]
88 pub fn dar(&self) -> DAR_R {
89 DAR_R::new(((self.bits >> 5) & 1) != 0)
90 }
91 #[doc = "Bit 6 - Configuration Change Enable"]
92 #[inline(always)]
93 pub fn cce(&self) -> CCE_R {
94 CCE_R::new(((self.bits >> 6) & 1) != 0)
95 }
96 #[doc = "Bit 7 - Test Mode Enable Write"]
97 #[inline(always)]
98 pub fn test(&self) -> TEST_R {
99 TEST_R::new(((self.bits >> 7) & 1) != 0)
100 }
101}
102impl W {
103 #[doc = "Bit 0 - Initialize"]
104 #[inline(always)]
105 #[must_use]
106 pub fn init(&mut self) -> INIT_W<0> {
107 INIT_W::new(self)
108 }
109 #[doc = "Bit 1 - Module Interrupt Enable"]
110 #[inline(always)]
111 #[must_use]
112 pub fn ie(&mut self) -> IE_W<1> {
113 IE_W::new(self)
114 }
115 #[doc = "Bit 2 - Status Change Interrupt Enable"]
116 #[inline(always)]
117 #[must_use]
118 pub fn sie(&mut self) -> SIE_W<2> {
119 SIE_W::new(self)
120 }
121 #[doc = "Bit 3 - Error Interrupt Enable"]
122 #[inline(always)]
123 #[must_use]
124 pub fn eie(&mut self) -> EIE_W<3> {
125 EIE_W::new(self)
126 }
127 #[doc = "Bit 5 - Disable Automatic Retransmission"]
128 #[inline(always)]
129 #[must_use]
130 pub fn dar(&mut self) -> DAR_W<5> {
131 DAR_W::new(self)
132 }
133 #[doc = "Bit 6 - Configuration Change Enable"]
134 #[inline(always)]
135 #[must_use]
136 pub fn cce(&mut self) -> CCE_W<6> {
137 CCE_W::new(self)
138 }
139 #[doc = "Bit 7 - Test Mode Enable Write"]
140 #[inline(always)]
141 #[must_use]
142 pub fn test(&mut self) -> TEST_W<7> {
143 TEST_W::new(self)
144 }
145 #[doc = "Writes raw bits to the register."]
146 #[inline(always)]
147 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
148 self.0.bits(bits);
149 self
150 }
151}
152#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
153pub struct CTRL_SPEC;
154impl crate::RegisterSpec for CTRL_SPEC {
155 type Ux = u32;
156}
157#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
158impl crate::Readable for CTRL_SPEC {
159 type Reader = R;
160}
161#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
162impl crate::Writable for CTRL_SPEC {
163 type Writer = W;
164 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
165 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
166}
167#[doc = "`reset()` method sets CTRL to value 0x01"]
168impl crate::Resettable for CTRL_SPEC {
169 const RESET_VALUE: Self::Ux = 0x01;
170}