efm32tg11b_pac/efm32tg11b120/vdac0/
opa0_ctrl.rs

1#[doc = "Register `OPA0_CTRL` reader"]
2pub struct R(crate::R<OPA0_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<OPA0_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<OPA0_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<OPA0_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `OPA0_CTRL` writer"]
17pub struct W(crate::W<OPA0_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<OPA0_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<OPA0_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<OPA0_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DRIVESTRENGTH` reader - OPAx Operation Mode"]
38pub type DRIVESTRENGTH_R = crate::FieldReader<u8, DRIVESTRENGTH_A>;
39#[doc = "OPAx Operation Mode\n\nValue on reset: 2"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum DRIVESTRENGTH_A {
43    #[doc = "0: Lower accuracy with Low drive strength."]
44    _0 = 0,
45    #[doc = "1: Low accuracy with Low drive strength."]
46    _1 = 1,
47    #[doc = "2: High accuracy with High drive strength."]
48    _2 = 2,
49    #[doc = "3: Higher accuracy with High drive strength."]
50    _3 = 3,
51}
52impl From<DRIVESTRENGTH_A> for u8 {
53    #[inline(always)]
54    fn from(variant: DRIVESTRENGTH_A) -> Self {
55        variant as _
56    }
57}
58impl DRIVESTRENGTH_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> DRIVESTRENGTH_A {
62        match self.bits {
63            0 => DRIVESTRENGTH_A::_0,
64            1 => DRIVESTRENGTH_A::_1,
65            2 => DRIVESTRENGTH_A::_2,
66            3 => DRIVESTRENGTH_A::_3,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `_0`"]
71    #[inline(always)]
72    pub fn is_0(&self) -> bool {
73        *self == DRIVESTRENGTH_A::_0
74    }
75    #[doc = "Checks if the value of the field is `_1`"]
76    #[inline(always)]
77    pub fn is_1(&self) -> bool {
78        *self == DRIVESTRENGTH_A::_1
79    }
80    #[doc = "Checks if the value of the field is `_2`"]
81    #[inline(always)]
82    pub fn is_2(&self) -> bool {
83        *self == DRIVESTRENGTH_A::_2
84    }
85    #[doc = "Checks if the value of the field is `_3`"]
86    #[inline(always)]
87    pub fn is_3(&self) -> bool {
88        *self == DRIVESTRENGTH_A::_3
89    }
90}
91#[doc = "Field `DRIVESTRENGTH` writer - OPAx Operation Mode"]
92pub type DRIVESTRENGTH_W<'a, const O: u8> =
93    crate::FieldWriterSafe<'a, u32, OPA0_CTRL_SPEC, u8, DRIVESTRENGTH_A, 2, O>;
94impl<'a, const O: u8> DRIVESTRENGTH_W<'a, O> {
95    #[doc = "Lower accuracy with Low drive strength."]
96    #[inline(always)]
97    pub fn _0(self) -> &'a mut W {
98        self.variant(DRIVESTRENGTH_A::_0)
99    }
100    #[doc = "Low accuracy with Low drive strength."]
101    #[inline(always)]
102    pub fn _1(self) -> &'a mut W {
103        self.variant(DRIVESTRENGTH_A::_1)
104    }
105    #[doc = "High accuracy with High drive strength."]
106    #[inline(always)]
107    pub fn _2(self) -> &'a mut W {
108        self.variant(DRIVESTRENGTH_A::_2)
109    }
110    #[doc = "Higher accuracy with High drive strength."]
111    #[inline(always)]
112    pub fn _3(self) -> &'a mut W {
113        self.variant(DRIVESTRENGTH_A::_3)
114    }
115}
116#[doc = "Field `INCBW` reader - OPAx Unity Gain Bandwidth Scale"]
117pub type INCBW_R = crate::BitReader<bool>;
118#[doc = "Field `INCBW` writer - OPAx Unity Gain Bandwidth Scale"]
119pub type INCBW_W<'a, const O: u8> = crate::BitWriter<'a, u32, OPA0_CTRL_SPEC, bool, O>;
120#[doc = "Field `HCMDIS` reader - High Common Mode Disable"]
121pub type HCMDIS_R = crate::BitReader<bool>;
122#[doc = "Field `HCMDIS` writer - High Common Mode Disable"]
123pub type HCMDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, OPA0_CTRL_SPEC, bool, O>;
124#[doc = "Field `OUTSCALE` reader - Scale OPAx Output Driving Strength"]
125pub type OUTSCALE_R = crate::BitReader<bool>;
126#[doc = "Field `OUTSCALE` writer - Scale OPAx Output Driving Strength"]
127pub type OUTSCALE_W<'a, const O: u8> = crate::BitWriter<'a, u32, OPA0_CTRL_SPEC, bool, O>;
128#[doc = "Field `PRSEN` reader - OPAx PRS Trigger Enable"]
129pub type PRSEN_R = crate::BitReader<bool>;
130#[doc = "Field `PRSEN` writer - OPAx PRS Trigger Enable"]
131pub type PRSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OPA0_CTRL_SPEC, bool, O>;
132#[doc = "Field `PRSMODE` reader - OPAx PRS Trigger Mode"]
133pub type PRSMODE_R = crate::BitReader<bool>;
134#[doc = "Field `PRSMODE` writer - OPAx PRS Trigger Mode"]
135pub type PRSMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, OPA0_CTRL_SPEC, bool, O>;
136#[doc = "Field `PRSSEL` reader - OPAx PRS Trigger Select"]
137pub type PRSSEL_R = crate::FieldReader<u8, PRSSEL_A>;
138#[doc = "OPAx PRS Trigger Select\n\nValue on reset: 0"]
139#[derive(Clone, Copy, Debug, PartialEq, Eq)]
140#[repr(u8)]
141pub enum PRSSEL_A {
142    #[doc = "0: PRS ch 0 triggers OPA."]
143    PRSCH0 = 0,
144    #[doc = "1: PRS ch 1 triggers OPA."]
145    PRSCH1 = 1,
146    #[doc = "2: PRS ch 2 triggers OPA."]
147    PRSCH2 = 2,
148    #[doc = "3: PRS ch 3 triggers OPA."]
149    PRSCH3 = 3,
150    #[doc = "4: PRS ch 4 triggers OPA."]
151    PRSCH4 = 4,
152    #[doc = "5: PRS ch 5 triggers OPA."]
153    PRSCH5 = 5,
154    #[doc = "6: PRS ch 6 triggers OPA."]
155    PRSCH6 = 6,
156    #[doc = "7: PRS ch 7 triggers OPA."]
157    PRSCH7 = 7,
158}
159impl From<PRSSEL_A> for u8 {
160    #[inline(always)]
161    fn from(variant: PRSSEL_A) -> Self {
162        variant as _
163    }
164}
165impl PRSSEL_R {
166    #[doc = "Get enumerated values variant"]
167    #[inline(always)]
168    pub fn variant(&self) -> PRSSEL_A {
169        match self.bits {
170            0 => PRSSEL_A::PRSCH0,
171            1 => PRSSEL_A::PRSCH1,
172            2 => PRSSEL_A::PRSCH2,
173            3 => PRSSEL_A::PRSCH3,
174            4 => PRSSEL_A::PRSCH4,
175            5 => PRSSEL_A::PRSCH5,
176            6 => PRSSEL_A::PRSCH6,
177            7 => PRSSEL_A::PRSCH7,
178            _ => unreachable!(),
179        }
180    }
181    #[doc = "Checks if the value of the field is `PRSCH0`"]
182    #[inline(always)]
183    pub fn is_prsch0(&self) -> bool {
184        *self == PRSSEL_A::PRSCH0
185    }
186    #[doc = "Checks if the value of the field is `PRSCH1`"]
187    #[inline(always)]
188    pub fn is_prsch1(&self) -> bool {
189        *self == PRSSEL_A::PRSCH1
190    }
191    #[doc = "Checks if the value of the field is `PRSCH2`"]
192    #[inline(always)]
193    pub fn is_prsch2(&self) -> bool {
194        *self == PRSSEL_A::PRSCH2
195    }
196    #[doc = "Checks if the value of the field is `PRSCH3`"]
197    #[inline(always)]
198    pub fn is_prsch3(&self) -> bool {
199        *self == PRSSEL_A::PRSCH3
200    }
201    #[doc = "Checks if the value of the field is `PRSCH4`"]
202    #[inline(always)]
203    pub fn is_prsch4(&self) -> bool {
204        *self == PRSSEL_A::PRSCH4
205    }
206    #[doc = "Checks if the value of the field is `PRSCH5`"]
207    #[inline(always)]
208    pub fn is_prsch5(&self) -> bool {
209        *self == PRSSEL_A::PRSCH5
210    }
211    #[doc = "Checks if the value of the field is `PRSCH6`"]
212    #[inline(always)]
213    pub fn is_prsch6(&self) -> bool {
214        *self == PRSSEL_A::PRSCH6
215    }
216    #[doc = "Checks if the value of the field is `PRSCH7`"]
217    #[inline(always)]
218    pub fn is_prsch7(&self) -> bool {
219        *self == PRSSEL_A::PRSCH7
220    }
221}
222#[doc = "Field `PRSSEL` writer - OPAx PRS Trigger Select"]
223pub type PRSSEL_W<'a, const O: u8> =
224    crate::FieldWriterSafe<'a, u32, OPA0_CTRL_SPEC, u8, PRSSEL_A, 3, O>;
225impl<'a, const O: u8> PRSSEL_W<'a, O> {
226    #[doc = "PRS ch 0 triggers OPA."]
227    #[inline(always)]
228    pub fn prsch0(self) -> &'a mut W {
229        self.variant(PRSSEL_A::PRSCH0)
230    }
231    #[doc = "PRS ch 1 triggers OPA."]
232    #[inline(always)]
233    pub fn prsch1(self) -> &'a mut W {
234        self.variant(PRSSEL_A::PRSCH1)
235    }
236    #[doc = "PRS ch 2 triggers OPA."]
237    #[inline(always)]
238    pub fn prsch2(self) -> &'a mut W {
239        self.variant(PRSSEL_A::PRSCH2)
240    }
241    #[doc = "PRS ch 3 triggers OPA."]
242    #[inline(always)]
243    pub fn prsch3(self) -> &'a mut W {
244        self.variant(PRSSEL_A::PRSCH3)
245    }
246    #[doc = "PRS ch 4 triggers OPA."]
247    #[inline(always)]
248    pub fn prsch4(self) -> &'a mut W {
249        self.variant(PRSSEL_A::PRSCH4)
250    }
251    #[doc = "PRS ch 5 triggers OPA."]
252    #[inline(always)]
253    pub fn prsch5(self) -> &'a mut W {
254        self.variant(PRSSEL_A::PRSCH5)
255    }
256    #[doc = "PRS ch 6 triggers OPA."]
257    #[inline(always)]
258    pub fn prsch6(self) -> &'a mut W {
259        self.variant(PRSSEL_A::PRSCH6)
260    }
261    #[doc = "PRS ch 7 triggers OPA."]
262    #[inline(always)]
263    pub fn prsch7(self) -> &'a mut W {
264        self.variant(PRSSEL_A::PRSCH7)
265    }
266}
267#[doc = "Field `PRSOUTMODE` reader - OPAx PRS Output Select"]
268pub type PRSOUTMODE_R = crate::BitReader<bool>;
269#[doc = "Field `PRSOUTMODE` writer - OPAx PRS Output Select"]
270pub type PRSOUTMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, OPA0_CTRL_SPEC, bool, O>;
271#[doc = "Field `APORTXMASTERDIS` reader - APORT Bus Master Disable"]
272pub type APORTXMASTERDIS_R = crate::BitReader<bool>;
273#[doc = "Field `APORTXMASTERDIS` writer - APORT Bus Master Disable"]
274pub type APORTXMASTERDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, OPA0_CTRL_SPEC, bool, O>;
275#[doc = "Field `APORTYMASTERDIS` reader - APORT Bus Master Disable"]
276pub type APORTYMASTERDIS_R = crate::BitReader<bool>;
277#[doc = "Field `APORTYMASTERDIS` writer - APORT Bus Master Disable"]
278pub type APORTYMASTERDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, OPA0_CTRL_SPEC, bool, O>;
279impl R {
280    #[doc = "Bits 0:1 - OPAx Operation Mode"]
281    #[inline(always)]
282    pub fn drivestrength(&self) -> DRIVESTRENGTH_R {
283        DRIVESTRENGTH_R::new((self.bits & 3) as u8)
284    }
285    #[doc = "Bit 2 - OPAx Unity Gain Bandwidth Scale"]
286    #[inline(always)]
287    pub fn incbw(&self) -> INCBW_R {
288        INCBW_R::new(((self.bits >> 2) & 1) != 0)
289    }
290    #[doc = "Bit 3 - High Common Mode Disable"]
291    #[inline(always)]
292    pub fn hcmdis(&self) -> HCMDIS_R {
293        HCMDIS_R::new(((self.bits >> 3) & 1) != 0)
294    }
295    #[doc = "Bit 4 - Scale OPAx Output Driving Strength"]
296    #[inline(always)]
297    pub fn outscale(&self) -> OUTSCALE_R {
298        OUTSCALE_R::new(((self.bits >> 4) & 1) != 0)
299    }
300    #[doc = "Bit 8 - OPAx PRS Trigger Enable"]
301    #[inline(always)]
302    pub fn prsen(&self) -> PRSEN_R {
303        PRSEN_R::new(((self.bits >> 8) & 1) != 0)
304    }
305    #[doc = "Bit 9 - OPAx PRS Trigger Mode"]
306    #[inline(always)]
307    pub fn prsmode(&self) -> PRSMODE_R {
308        PRSMODE_R::new(((self.bits >> 9) & 1) != 0)
309    }
310    #[doc = "Bits 10:12 - OPAx PRS Trigger Select"]
311    #[inline(always)]
312    pub fn prssel(&self) -> PRSSEL_R {
313        PRSSEL_R::new(((self.bits >> 10) & 7) as u8)
314    }
315    #[doc = "Bit 16 - OPAx PRS Output Select"]
316    #[inline(always)]
317    pub fn prsoutmode(&self) -> PRSOUTMODE_R {
318        PRSOUTMODE_R::new(((self.bits >> 16) & 1) != 0)
319    }
320    #[doc = "Bit 20 - APORT Bus Master Disable"]
321    #[inline(always)]
322    pub fn aportxmasterdis(&self) -> APORTXMASTERDIS_R {
323        APORTXMASTERDIS_R::new(((self.bits >> 20) & 1) != 0)
324    }
325    #[doc = "Bit 21 - APORT Bus Master Disable"]
326    #[inline(always)]
327    pub fn aportymasterdis(&self) -> APORTYMASTERDIS_R {
328        APORTYMASTERDIS_R::new(((self.bits >> 21) & 1) != 0)
329    }
330}
331impl W {
332    #[doc = "Bits 0:1 - OPAx Operation Mode"]
333    #[inline(always)]
334    #[must_use]
335    pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<0> {
336        DRIVESTRENGTH_W::new(self)
337    }
338    #[doc = "Bit 2 - OPAx Unity Gain Bandwidth Scale"]
339    #[inline(always)]
340    #[must_use]
341    pub fn incbw(&mut self) -> INCBW_W<2> {
342        INCBW_W::new(self)
343    }
344    #[doc = "Bit 3 - High Common Mode Disable"]
345    #[inline(always)]
346    #[must_use]
347    pub fn hcmdis(&mut self) -> HCMDIS_W<3> {
348        HCMDIS_W::new(self)
349    }
350    #[doc = "Bit 4 - Scale OPAx Output Driving Strength"]
351    #[inline(always)]
352    #[must_use]
353    pub fn outscale(&mut self) -> OUTSCALE_W<4> {
354        OUTSCALE_W::new(self)
355    }
356    #[doc = "Bit 8 - OPAx PRS Trigger Enable"]
357    #[inline(always)]
358    #[must_use]
359    pub fn prsen(&mut self) -> PRSEN_W<8> {
360        PRSEN_W::new(self)
361    }
362    #[doc = "Bit 9 - OPAx PRS Trigger Mode"]
363    #[inline(always)]
364    #[must_use]
365    pub fn prsmode(&mut self) -> PRSMODE_W<9> {
366        PRSMODE_W::new(self)
367    }
368    #[doc = "Bits 10:12 - OPAx PRS Trigger Select"]
369    #[inline(always)]
370    #[must_use]
371    pub fn prssel(&mut self) -> PRSSEL_W<10> {
372        PRSSEL_W::new(self)
373    }
374    #[doc = "Bit 16 - OPAx PRS Output Select"]
375    #[inline(always)]
376    #[must_use]
377    pub fn prsoutmode(&mut self) -> PRSOUTMODE_W<16> {
378        PRSOUTMODE_W::new(self)
379    }
380    #[doc = "Bit 20 - APORT Bus Master Disable"]
381    #[inline(always)]
382    #[must_use]
383    pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W<20> {
384        APORTXMASTERDIS_W::new(self)
385    }
386    #[doc = "Bit 21 - APORT Bus Master Disable"]
387    #[inline(always)]
388    #[must_use]
389    pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W<21> {
390        APORTYMASTERDIS_W::new(self)
391    }
392    #[doc = "Writes raw bits to the register."]
393    #[inline(always)]
394    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
395        self.0.bits(bits);
396        self
397    }
398}
399#[doc = "Operational Amplifier Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opa0_ctrl](index.html) module"]
400pub struct OPA0_CTRL_SPEC;
401impl crate::RegisterSpec for OPA0_CTRL_SPEC {
402    type Ux = u32;
403}
404#[doc = "`read()` method returns [opa0_ctrl::R](R) reader structure"]
405impl crate::Readable for OPA0_CTRL_SPEC {
406    type Reader = R;
407}
408#[doc = "`write(|w| ..)` method takes [opa0_ctrl::W](W) writer structure"]
409impl crate::Writable for OPA0_CTRL_SPEC {
410    type Writer = W;
411    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
412    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
413}
414#[doc = "`reset()` method sets OPA0_CTRL to value 0x0e"]
415impl crate::Resettable for OPA0_CTRL_SPEC {
416    const RESET_VALUE: Self::Ux = 0x0e;
417}
efm32tg11b_pac/efm32tg11b120/vdac0/opa0_ctrl.rs

efm32tg11b_pac/efm32tg11b120/vdac0/
opa0_ctrl.rs
