efm32tg11b_pac/efm32tg11b120/prs/
swpulse.rs

1#[doc = "Register `SWPULSE` writer"]
2pub struct W(crate::W<SWPULSE_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<SWPULSE_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<SWPULSE_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<SWPULSE_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `CH0PULSE` writer - Channel 0 Pulse Generation"]
23pub type CH0PULSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWPULSE_SPEC, bool, O>;
24#[doc = "Field `CH1PULSE` writer - Channel 1 Pulse Generation"]
25pub type CH1PULSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWPULSE_SPEC, bool, O>;
26#[doc = "Field `CH2PULSE` writer - Channel 2 Pulse Generation"]
27pub type CH2PULSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWPULSE_SPEC, bool, O>;
28#[doc = "Field `CH3PULSE` writer - Channel 3 Pulse Generation"]
29pub type CH3PULSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWPULSE_SPEC, bool, O>;
30#[doc = "Field `CH4PULSE` writer - Channel 4 Pulse Generation"]
31pub type CH4PULSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWPULSE_SPEC, bool, O>;
32#[doc = "Field `CH5PULSE` writer - Channel 5 Pulse Generation"]
33pub type CH5PULSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWPULSE_SPEC, bool, O>;
34#[doc = "Field `CH6PULSE` writer - Channel 6 Pulse Generation"]
35pub type CH6PULSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWPULSE_SPEC, bool, O>;
36#[doc = "Field `CH7PULSE` writer - Channel 7 Pulse Generation"]
37pub type CH7PULSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWPULSE_SPEC, bool, O>;
38impl W {
39    #[doc = "Bit 0 - Channel 0 Pulse Generation"]
40    #[inline(always)]
41    #[must_use]
42    pub fn ch0pulse(&mut self) -> CH0PULSE_W<0> {
43        CH0PULSE_W::new(self)
44    }
45    #[doc = "Bit 1 - Channel 1 Pulse Generation"]
46    #[inline(always)]
47    #[must_use]
48    pub fn ch1pulse(&mut self) -> CH1PULSE_W<1> {
49        CH1PULSE_W::new(self)
50    }
51    #[doc = "Bit 2 - Channel 2 Pulse Generation"]
52    #[inline(always)]
53    #[must_use]
54    pub fn ch2pulse(&mut self) -> CH2PULSE_W<2> {
55        CH2PULSE_W::new(self)
56    }
57    #[doc = "Bit 3 - Channel 3 Pulse Generation"]
58    #[inline(always)]
59    #[must_use]
60    pub fn ch3pulse(&mut self) -> CH3PULSE_W<3> {
61        CH3PULSE_W::new(self)
62    }
63    #[doc = "Bit 4 - Channel 4 Pulse Generation"]
64    #[inline(always)]
65    #[must_use]
66    pub fn ch4pulse(&mut self) -> CH4PULSE_W<4> {
67        CH4PULSE_W::new(self)
68    }
69    #[doc = "Bit 5 - Channel 5 Pulse Generation"]
70    #[inline(always)]
71    #[must_use]
72    pub fn ch5pulse(&mut self) -> CH5PULSE_W<5> {
73        CH5PULSE_W::new(self)
74    }
75    #[doc = "Bit 6 - Channel 6 Pulse Generation"]
76    #[inline(always)]
77    #[must_use]
78    pub fn ch6pulse(&mut self) -> CH6PULSE_W<6> {
79        CH6PULSE_W::new(self)
80    }
81    #[doc = "Bit 7 - Channel 7 Pulse Generation"]
82    #[inline(always)]
83    #[must_use]
84    pub fn ch7pulse(&mut self) -> CH7PULSE_W<7> {
85        CH7PULSE_W::new(self)
86    }
87    #[doc = "Writes raw bits to the register."]
88    #[inline(always)]
89    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
90        self.0.bits(bits);
91        self
92    }
93}
94#[doc = "Software Pulse Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swpulse](index.html) module"]
95pub struct SWPULSE_SPEC;
96impl crate::RegisterSpec for SWPULSE_SPEC {
97    type Ux = u32;
98}
99#[doc = "`write(|w| ..)` method takes [swpulse::W](W) writer structure"]
100impl crate::Writable for SWPULSE_SPEC {
101    type Writer = W;
102    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
103    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
104}
105#[doc = "`reset()` method sets SWPULSE to value 0"]
106impl crate::Resettable for SWPULSE_SPEC {
107    const RESET_VALUE: Self::Ux = 0;
108}
efm32tg11b_pac/efm32tg11b120/prs/swpulse.rs

efm32tg11b_pac/efm32tg11b120/prs/
swpulse.rs
