efm32tg11b_pac/efm32tg11b120/emu/
vmonio0ctrl.rs

1#[doc = "Register `VMONIO0CTRL` reader"]
2pub struct R(crate::R<VMONIO0CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<VMONIO0CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<VMONIO0CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<VMONIO0CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `VMONIO0CTRL` writer"]
17pub struct W(crate::W<VMONIO0CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<VMONIO0CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<VMONIO0CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<VMONIO0CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `EN` reader - Enable"]
38pub type EN_R = crate::BitReader<bool>;
39#[doc = "Field `EN` writer - Enable"]
40pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, VMONIO0CTRL_SPEC, bool, O>;
41#[doc = "Field `RISEWU` reader - Rise Wakeup"]
42pub type RISEWU_R = crate::BitReader<bool>;
43#[doc = "Field `RISEWU` writer - Rise Wakeup"]
44pub type RISEWU_W<'a, const O: u8> = crate::BitWriter<'a, u32, VMONIO0CTRL_SPEC, bool, O>;
45#[doc = "Field `FALLWU` reader - Fall Wakeup"]
46pub type FALLWU_R = crate::BitReader<bool>;
47#[doc = "Field `FALLWU` writer - Fall Wakeup"]
48pub type FALLWU_W<'a, const O: u8> = crate::BitWriter<'a, u32, VMONIO0CTRL_SPEC, bool, O>;
49#[doc = "Field `RETDIS` reader - EM4 IO0 Retention Disable"]
50pub type RETDIS_R = crate::BitReader<bool>;
51#[doc = "Field `RETDIS` writer - EM4 IO0 Retention Disable"]
52pub type RETDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, VMONIO0CTRL_SPEC, bool, O>;
53#[doc = "Field `THRESFINE` reader - Threshold Fine Adjust"]
54pub type THRESFINE_R = crate::FieldReader<u8, u8>;
55#[doc = "Field `THRESFINE` writer - Threshold Fine Adjust"]
56pub type THRESFINE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, VMONIO0CTRL_SPEC, u8, u8, 4, O>;
57#[doc = "Field `THRESCOARSE` reader - Threshold Coarse Adjust"]
58pub type THRESCOARSE_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `THRESCOARSE` writer - Threshold Coarse Adjust"]
60pub type THRESCOARSE_W<'a, const O: u8> =
61    crate::FieldWriter<'a, u32, VMONIO0CTRL_SPEC, u8, u8, 4, O>;
62impl R {
63    #[doc = "Bit 0 - Enable"]
64    #[inline(always)]
65    pub fn en(&self) -> EN_R {
66        EN_R::new((self.bits & 1) != 0)
67    }
68    #[doc = "Bit 2 - Rise Wakeup"]
69    #[inline(always)]
70    pub fn risewu(&self) -> RISEWU_R {
71        RISEWU_R::new(((self.bits >> 2) & 1) != 0)
72    }
73    #[doc = "Bit 3 - Fall Wakeup"]
74    #[inline(always)]
75    pub fn fallwu(&self) -> FALLWU_R {
76        FALLWU_R::new(((self.bits >> 3) & 1) != 0)
77    }
78    #[doc = "Bit 4 - EM4 IO0 Retention Disable"]
79    #[inline(always)]
80    pub fn retdis(&self) -> RETDIS_R {
81        RETDIS_R::new(((self.bits >> 4) & 1) != 0)
82    }
83    #[doc = "Bits 8:11 - Threshold Fine Adjust"]
84    #[inline(always)]
85    pub fn thresfine(&self) -> THRESFINE_R {
86        THRESFINE_R::new(((self.bits >> 8) & 0x0f) as u8)
87    }
88    #[doc = "Bits 12:15 - Threshold Coarse Adjust"]
89    #[inline(always)]
90    pub fn threscoarse(&self) -> THRESCOARSE_R {
91        THRESCOARSE_R::new(((self.bits >> 12) & 0x0f) as u8)
92    }
93}
94impl W {
95    #[doc = "Bit 0 - Enable"]
96    #[inline(always)]
97    #[must_use]
98    pub fn en(&mut self) -> EN_W<0> {
99        EN_W::new(self)
100    }
101    #[doc = "Bit 2 - Rise Wakeup"]
102    #[inline(always)]
103    #[must_use]
104    pub fn risewu(&mut self) -> RISEWU_W<2> {
105        RISEWU_W::new(self)
106    }
107    #[doc = "Bit 3 - Fall Wakeup"]
108    #[inline(always)]
109    #[must_use]
110    pub fn fallwu(&mut self) -> FALLWU_W<3> {
111        FALLWU_W::new(self)
112    }
113    #[doc = "Bit 4 - EM4 IO0 Retention Disable"]
114    #[inline(always)]
115    #[must_use]
116    pub fn retdis(&mut self) -> RETDIS_W<4> {
117        RETDIS_W::new(self)
118    }
119    #[doc = "Bits 8:11 - Threshold Fine Adjust"]
120    #[inline(always)]
121    #[must_use]
122    pub fn thresfine(&mut self) -> THRESFINE_W<8> {
123        THRESFINE_W::new(self)
124    }
125    #[doc = "Bits 12:15 - Threshold Coarse Adjust"]
126    #[inline(always)]
127    #[must_use]
128    pub fn threscoarse(&mut self) -> THRESCOARSE_W<12> {
129        THRESCOARSE_W::new(self)
130    }
131    #[doc = "Writes raw bits to the register."]
132    #[inline(always)]
133    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
134        self.0.bits(bits);
135        self
136    }
137}
138#[doc = "VMON IOVDD0 Channel Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vmonio0ctrl](index.html) module"]
139pub struct VMONIO0CTRL_SPEC;
140impl crate::RegisterSpec for VMONIO0CTRL_SPEC {
141    type Ux = u32;
142}
143#[doc = "`read()` method returns [vmonio0ctrl::R](R) reader structure"]
144impl crate::Readable for VMONIO0CTRL_SPEC {
145    type Reader = R;
146}
147#[doc = "`write(|w| ..)` method takes [vmonio0ctrl::W](W) writer structure"]
148impl crate::Writable for VMONIO0CTRL_SPEC {
149    type Writer = W;
150    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
151    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
152}
153#[doc = "`reset()` method sets VMONIO0CTRL to value 0"]
154impl crate::Resettable for VMONIO0CTRL_SPEC {
155    const RESET_VALUE: Self::Ux = 0;
156}
efm32tg11b_pac/efm32tg11b120/emu/vmonio0ctrl.rs

efm32tg11b_pac/efm32tg11b120/emu/
vmonio0ctrl.rs
