efm32tg11b_pac/efm32tg11b120/emu/
dcdclpctrl.rs

1#[doc = "Register `DCDCLPCTRL` reader"]
2pub struct R(crate::R<DCDCLPCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DCDCLPCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DCDCLPCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DCDCLPCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DCDCLPCTRL` writer"]
17pub struct W(crate::W<DCDCLPCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DCDCLPCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DCDCLPCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DCDCLPCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `LPCMPHYSSELEM234H` reader - LP Mode Hysteresis Selection for EM23 and EM4H"]
38pub type LPCMPHYSSELEM234H_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `LPCMPHYSSELEM234H` writer - LP Mode Hysteresis Selection for EM23 and EM4H"]
40pub type LPCMPHYSSELEM234H_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, DCDCLPCTRL_SPEC, u8, u8, 4, O>;
42#[doc = "Field `LPVREFDUTYEN` reader - LP Mode Duty Cycling Enable"]
43pub type LPVREFDUTYEN_R = crate::BitReader<bool>;
44#[doc = "Field `LPVREFDUTYEN` writer - LP Mode Duty Cycling Enable"]
45pub type LPVREFDUTYEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCDCLPCTRL_SPEC, bool, O>;
46#[doc = "Field `LPBLANK` reader - Reserved for internal use. Do not change."]
47pub type LPBLANK_R = crate::FieldReader<u8, u8>;
48#[doc = "Field `LPBLANK` writer - Reserved for internal use. Do not change."]
49pub type LPBLANK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCDCLPCTRL_SPEC, u8, u8, 2, O>;
50impl R {
51    #[doc = "Bits 12:15 - LP Mode Hysteresis Selection for EM23 and EM4H"]
52    #[inline(always)]
53    pub fn lpcmphysselem234h(&self) -> LPCMPHYSSELEM234H_R {
54        LPCMPHYSSELEM234H_R::new(((self.bits >> 12) & 0x0f) as u8)
55    }
56    #[doc = "Bit 24 - LP Mode Duty Cycling Enable"]
57    #[inline(always)]
58    pub fn lpvrefdutyen(&self) -> LPVREFDUTYEN_R {
59        LPVREFDUTYEN_R::new(((self.bits >> 24) & 1) != 0)
60    }
61    #[doc = "Bits 25:26 - Reserved for internal use. Do not change."]
62    #[inline(always)]
63    pub fn lpblank(&self) -> LPBLANK_R {
64        LPBLANK_R::new(((self.bits >> 25) & 3) as u8)
65    }
66}
67impl W {
68    #[doc = "Bits 12:15 - LP Mode Hysteresis Selection for EM23 and EM4H"]
69    #[inline(always)]
70    #[must_use]
71    pub fn lpcmphysselem234h(&mut self) -> LPCMPHYSSELEM234H_W<12> {
72        LPCMPHYSSELEM234H_W::new(self)
73    }
74    #[doc = "Bit 24 - LP Mode Duty Cycling Enable"]
75    #[inline(always)]
76    #[must_use]
77    pub fn lpvrefdutyen(&mut self) -> LPVREFDUTYEN_W<24> {
78        LPVREFDUTYEN_W::new(self)
79    }
80    #[doc = "Bits 25:26 - Reserved for internal use. Do not change."]
81    #[inline(always)]
82    #[must_use]
83    pub fn lpblank(&mut self) -> LPBLANK_W<25> {
84        LPBLANK_W::new(self)
85    }
86    #[doc = "Writes raw bits to the register."]
87    #[inline(always)]
88    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
89        self.0.bits(bits);
90        self
91    }
92}
93#[doc = "DCDC Low Power Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcdclpctrl](index.html) module"]
94pub struct DCDCLPCTRL_SPEC;
95impl crate::RegisterSpec for DCDCLPCTRL_SPEC {
96    type Ux = u32;
97}
98#[doc = "`read()` method returns [dcdclpctrl::R](R) reader structure"]
99impl crate::Readable for DCDCLPCTRL_SPEC {
100    type Reader = R;
101}
102#[doc = "`write(|w| ..)` method takes [dcdclpctrl::W](W) writer structure"]
103impl crate::Writable for DCDCLPCTRL_SPEC {
104    type Writer = W;
105    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
106    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
107}
108#[doc = "`reset()` method sets DCDCLPCTRL to value 0x0300_0000"]
109impl crate::Resettable for DCDCLPCTRL_SPEC {
110    const RESET_VALUE: Self::Ux = 0x0300_0000;
111}
efm32tg11b_pac/efm32tg11b120/emu/dcdclpctrl.rs

efm32tg11b_pac/efm32tg11b120/emu/
dcdclpctrl.rs
