1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `AES` reader - AES Mode"]
38pub type AES_R = crate::BitReader<bool>;
39#[doc = "Field `AES` writer - AES Mode"]
40pub type AES_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
41#[doc = "Field `KEYBUFDIS` reader - Key Buffer Disable"]
42pub type KEYBUFDIS_R = crate::BitReader<bool>;
43#[doc = "Field `KEYBUFDIS` writer - Key Buffer Disable"]
44pub type KEYBUFDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
45#[doc = "Field `SHA` reader - SHA Mode"]
46pub type SHA_R = crate::BitReader<bool>;
47#[doc = "Field `SHA` writer - SHA Mode"]
48pub type SHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
49#[doc = "Field `NOBUSYSTALL` reader - No Stalling of Bus When Busy"]
50pub type NOBUSYSTALL_R = crate::BitReader<bool>;
51#[doc = "Field `NOBUSYSTALL` writer - No Stalling of Bus When Busy"]
52pub type NOBUSYSTALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
53#[doc = "Field `INCWIDTH` reader - Increment Width"]
54pub type INCWIDTH_R = crate::FieldReader<u8, INCWIDTH_A>;
55#[doc = "Increment Width\n\nValue on reset: 0"]
56#[derive(Clone, Copy, Debug, PartialEq, Eq)]
57#[repr(u8)]
58pub enum INCWIDTH_A {
59 #[doc = "0: Byte 15 in DATA1 is used for the increment function."]
60 INCWIDTH1 = 0,
61 #[doc = "1: Bytes 14 and 15 in DATA1 are used for the increment function."]
62 INCWIDTH2 = 1,
63 #[doc = "2: Bytes 13 to 15 in DATA1 are used for the increment function."]
64 INCWIDTH3 = 2,
65 #[doc = "3: Bytes 12 to 15 in DATA1 are used for the increment function."]
66 INCWIDTH4 = 3,
67}
68impl From<INCWIDTH_A> for u8 {
69 #[inline(always)]
70 fn from(variant: INCWIDTH_A) -> Self {
71 variant as _
72 }
73}
74impl INCWIDTH_R {
75 #[doc = "Get enumerated values variant"]
76 #[inline(always)]
77 pub fn variant(&self) -> INCWIDTH_A {
78 match self.bits {
79 0 => INCWIDTH_A::INCWIDTH1,
80 1 => INCWIDTH_A::INCWIDTH2,
81 2 => INCWIDTH_A::INCWIDTH3,
82 3 => INCWIDTH_A::INCWIDTH4,
83 _ => unreachable!(),
84 }
85 }
86 #[doc = "Checks if the value of the field is `INCWIDTH1`"]
87 #[inline(always)]
88 pub fn is_incwidth1(&self) -> bool {
89 *self == INCWIDTH_A::INCWIDTH1
90 }
91 #[doc = "Checks if the value of the field is `INCWIDTH2`"]
92 #[inline(always)]
93 pub fn is_incwidth2(&self) -> bool {
94 *self == INCWIDTH_A::INCWIDTH2
95 }
96 #[doc = "Checks if the value of the field is `INCWIDTH3`"]
97 #[inline(always)]
98 pub fn is_incwidth3(&self) -> bool {
99 *self == INCWIDTH_A::INCWIDTH3
100 }
101 #[doc = "Checks if the value of the field is `INCWIDTH4`"]
102 #[inline(always)]
103 pub fn is_incwidth4(&self) -> bool {
104 *self == INCWIDTH_A::INCWIDTH4
105 }
106}
107#[doc = "Field `INCWIDTH` writer - Increment Width"]
108pub type INCWIDTH_W<'a, const O: u8> =
109 crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, INCWIDTH_A, 2, O>;
110impl<'a, const O: u8> INCWIDTH_W<'a, O> {
111 #[doc = "Byte 15 in DATA1 is used for the increment function."]
112 #[inline(always)]
113 pub fn incwidth1(self) -> &'a mut W {
114 self.variant(INCWIDTH_A::INCWIDTH1)
115 }
116 #[doc = "Bytes 14 and 15 in DATA1 are used for the increment function."]
117 #[inline(always)]
118 pub fn incwidth2(self) -> &'a mut W {
119 self.variant(INCWIDTH_A::INCWIDTH2)
120 }
121 #[doc = "Bytes 13 to 15 in DATA1 are used for the increment function."]
122 #[inline(always)]
123 pub fn incwidth3(self) -> &'a mut W {
124 self.variant(INCWIDTH_A::INCWIDTH3)
125 }
126 #[doc = "Bytes 12 to 15 in DATA1 are used for the increment function."]
127 #[inline(always)]
128 pub fn incwidth4(self) -> &'a mut W {
129 self.variant(INCWIDTH_A::INCWIDTH4)
130 }
131}
132#[doc = "Field `DMA0MODE` reader - DMA0 Read Mode"]
133pub type DMA0MODE_R = crate::FieldReader<u8, DMA0MODE_A>;
134#[doc = "DMA0 Read Mode\n\nValue on reset: 0"]
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136#[repr(u8)]
137pub enum DMA0MODE_A {
138 #[doc = "0: Target register is fully read/written during every DMA transaction"]
139 FULL = 0,
140 #[doc = "1: Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read. Zero padding is automatically added when writing."]
141 LENLIMIT = 1,
142 #[doc = "2: Target register is fully read/written during every DMA transaction. Bytewise DMA."]
143 FULLBYTE = 2,
144 #[doc = "3: Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing."]
145 LENLIMITBYTE = 3,
146}
147impl From<DMA0MODE_A> for u8 {
148 #[inline(always)]
149 fn from(variant: DMA0MODE_A) -> Self {
150 variant as _
151 }
152}
153impl DMA0MODE_R {
154 #[doc = "Get enumerated values variant"]
155 #[inline(always)]
156 pub fn variant(&self) -> DMA0MODE_A {
157 match self.bits {
158 0 => DMA0MODE_A::FULL,
159 1 => DMA0MODE_A::LENLIMIT,
160 2 => DMA0MODE_A::FULLBYTE,
161 3 => DMA0MODE_A::LENLIMITBYTE,
162 _ => unreachable!(),
163 }
164 }
165 #[doc = "Checks if the value of the field is `FULL`"]
166 #[inline(always)]
167 pub fn is_full(&self) -> bool {
168 *self == DMA0MODE_A::FULL
169 }
170 #[doc = "Checks if the value of the field is `LENLIMIT`"]
171 #[inline(always)]
172 pub fn is_lenlimit(&self) -> bool {
173 *self == DMA0MODE_A::LENLIMIT
174 }
175 #[doc = "Checks if the value of the field is `FULLBYTE`"]
176 #[inline(always)]
177 pub fn is_fullbyte(&self) -> bool {
178 *self == DMA0MODE_A::FULLBYTE
179 }
180 #[doc = "Checks if the value of the field is `LENLIMITBYTE`"]
181 #[inline(always)]
182 pub fn is_lenlimitbyte(&self) -> bool {
183 *self == DMA0MODE_A::LENLIMITBYTE
184 }
185}
186#[doc = "Field `DMA0MODE` writer - DMA0 Read Mode"]
187pub type DMA0MODE_W<'a, const O: u8> =
188 crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, DMA0MODE_A, 2, O>;
189impl<'a, const O: u8> DMA0MODE_W<'a, O> {
190 #[doc = "Target register is fully read/written during every DMA transaction"]
191 #[inline(always)]
192 pub fn full(self) -> &'a mut W {
193 self.variant(DMA0MODE_A::FULL)
194 }
195 #[doc = "Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read. Zero padding is automatically added when writing."]
196 #[inline(always)]
197 pub fn lenlimit(self) -> &'a mut W {
198 self.variant(DMA0MODE_A::LENLIMIT)
199 }
200 #[doc = "Target register is fully read/written during every DMA transaction. Bytewise DMA."]
201 #[inline(always)]
202 pub fn fullbyte(self) -> &'a mut W {
203 self.variant(DMA0MODE_A::FULLBYTE)
204 }
205 #[doc = "Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing."]
206 #[inline(always)]
207 pub fn lenlimitbyte(self) -> &'a mut W {
208 self.variant(DMA0MODE_A::LENLIMITBYTE)
209 }
210}
211#[doc = "Field `DMA0RSEL` reader - DMA0 Read Register Select"]
212pub type DMA0RSEL_R = crate::FieldReader<u8, DMA0RSEL_A>;
213#[doc = "DMA0 Read Register Select\n\nValue on reset: 0"]
214#[derive(Clone, Copy, Debug, PartialEq, Eq)]
215#[repr(u8)]
216pub enum DMA0RSEL_A {
217 #[doc = "0: `0`"]
218 DATA0 = 0,
219 #[doc = "1: `1`"]
220 DDATA0 = 1,
221 #[doc = "2: `10`"]
222 DDATA0BIG = 2,
223 #[doc = "3: `11`"]
224 QDATA0 = 3,
225}
226impl From<DMA0RSEL_A> for u8 {
227 #[inline(always)]
228 fn from(variant: DMA0RSEL_A) -> Self {
229 variant as _
230 }
231}
232impl DMA0RSEL_R {
233 #[doc = "Get enumerated values variant"]
234 #[inline(always)]
235 pub fn variant(&self) -> DMA0RSEL_A {
236 match self.bits {
237 0 => DMA0RSEL_A::DATA0,
238 1 => DMA0RSEL_A::DDATA0,
239 2 => DMA0RSEL_A::DDATA0BIG,
240 3 => DMA0RSEL_A::QDATA0,
241 _ => unreachable!(),
242 }
243 }
244 #[doc = "Checks if the value of the field is `DATA0`"]
245 #[inline(always)]
246 pub fn is_data0(&self) -> bool {
247 *self == DMA0RSEL_A::DATA0
248 }
249 #[doc = "Checks if the value of the field is `DDATA0`"]
250 #[inline(always)]
251 pub fn is_ddata0(&self) -> bool {
252 *self == DMA0RSEL_A::DDATA0
253 }
254 #[doc = "Checks if the value of the field is `DDATA0BIG`"]
255 #[inline(always)]
256 pub fn is_ddata0big(&self) -> bool {
257 *self == DMA0RSEL_A::DDATA0BIG
258 }
259 #[doc = "Checks if the value of the field is `QDATA0`"]
260 #[inline(always)]
261 pub fn is_qdata0(&self) -> bool {
262 *self == DMA0RSEL_A::QDATA0
263 }
264}
265#[doc = "Field `DMA0RSEL` writer - DMA0 Read Register Select"]
266pub type DMA0RSEL_W<'a, const O: u8> =
267 crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, DMA0RSEL_A, 2, O>;
268impl<'a, const O: u8> DMA0RSEL_W<'a, O> {
269 #[doc = "`0`"]
270 #[inline(always)]
271 pub fn data0(self) -> &'a mut W {
272 self.variant(DMA0RSEL_A::DATA0)
273 }
274 #[doc = "`1`"]
275 #[inline(always)]
276 pub fn ddata0(self) -> &'a mut W {
277 self.variant(DMA0RSEL_A::DDATA0)
278 }
279 #[doc = "`10`"]
280 #[inline(always)]
281 pub fn ddata0big(self) -> &'a mut W {
282 self.variant(DMA0RSEL_A::DDATA0BIG)
283 }
284 #[doc = "`11`"]
285 #[inline(always)]
286 pub fn qdata0(self) -> &'a mut W {
287 self.variant(DMA0RSEL_A::QDATA0)
288 }
289}
290#[doc = "Field `DMA1MODE` reader - DMA1 Read Mode"]
291pub type DMA1MODE_R = crate::FieldReader<u8, DMA1MODE_A>;
292#[doc = "DMA1 Read Mode\n\nValue on reset: 0"]
293#[derive(Clone, Copy, Debug, PartialEq, Eq)]
294#[repr(u8)]
295pub enum DMA1MODE_A {
296 #[doc = "0: Target register is fully read/written during every DMA transaction"]
297 FULL = 0,
298 #[doc = "1: Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Zero padding is automatically added when writing."]
299 LENLIMIT = 1,
300 #[doc = "2: Target register is fully read/written during every DMA transaction. Bytewise DMA."]
301 FULLBYTE = 2,
302 #[doc = "3: Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing."]
303 LENLIMITBYTE = 3,
304}
305impl From<DMA1MODE_A> for u8 {
306 #[inline(always)]
307 fn from(variant: DMA1MODE_A) -> Self {
308 variant as _
309 }
310}
311impl DMA1MODE_R {
312 #[doc = "Get enumerated values variant"]
313 #[inline(always)]
314 pub fn variant(&self) -> DMA1MODE_A {
315 match self.bits {
316 0 => DMA1MODE_A::FULL,
317 1 => DMA1MODE_A::LENLIMIT,
318 2 => DMA1MODE_A::FULLBYTE,
319 3 => DMA1MODE_A::LENLIMITBYTE,
320 _ => unreachable!(),
321 }
322 }
323 #[doc = "Checks if the value of the field is `FULL`"]
324 #[inline(always)]
325 pub fn is_full(&self) -> bool {
326 *self == DMA1MODE_A::FULL
327 }
328 #[doc = "Checks if the value of the field is `LENLIMIT`"]
329 #[inline(always)]
330 pub fn is_lenlimit(&self) -> bool {
331 *self == DMA1MODE_A::LENLIMIT
332 }
333 #[doc = "Checks if the value of the field is `FULLBYTE`"]
334 #[inline(always)]
335 pub fn is_fullbyte(&self) -> bool {
336 *self == DMA1MODE_A::FULLBYTE
337 }
338 #[doc = "Checks if the value of the field is `LENLIMITBYTE`"]
339 #[inline(always)]
340 pub fn is_lenlimitbyte(&self) -> bool {
341 *self == DMA1MODE_A::LENLIMITBYTE
342 }
343}
344#[doc = "Field `DMA1MODE` writer - DMA1 Read Mode"]
345pub type DMA1MODE_W<'a, const O: u8> =
346 crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, DMA1MODE_A, 2, O>;
347impl<'a, const O: u8> DMA1MODE_W<'a, O> {
348 #[doc = "Target register is fully read/written during every DMA transaction"]
349 #[inline(always)]
350 pub fn full(self) -> &'a mut W {
351 self.variant(DMA1MODE_A::FULL)
352 }
353 #[doc = "Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Zero padding is automatically added when writing."]
354 #[inline(always)]
355 pub fn lenlimit(self) -> &'a mut W {
356 self.variant(DMA1MODE_A::LENLIMIT)
357 }
358 #[doc = "Target register is fully read/written during every DMA transaction. Bytewise DMA."]
359 #[inline(always)]
360 pub fn fullbyte(self) -> &'a mut W {
361 self.variant(DMA1MODE_A::FULLBYTE)
362 }
363 #[doc = "Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing."]
364 #[inline(always)]
365 pub fn lenlimitbyte(self) -> &'a mut W {
366 self.variant(DMA1MODE_A::LENLIMITBYTE)
367 }
368}
369#[doc = "Field `DMA1RSEL` reader - DATA0 DMA Unaligned Read Register Select"]
370pub type DMA1RSEL_R = crate::FieldReader<u8, DMA1RSEL_A>;
371#[doc = "DATA0 DMA Unaligned Read Register Select\n\nValue on reset: 0"]
372#[derive(Clone, Copy, Debug, PartialEq, Eq)]
373#[repr(u8)]
374pub enum DMA1RSEL_A {
375 #[doc = "0: `0`"]
376 DATA1 = 0,
377 #[doc = "1: `1`"]
378 DDATA1 = 1,
379 #[doc = "2: `10`"]
380 QDATA1 = 2,
381 #[doc = "3: `11`"]
382 QDATA1BIG = 3,
383}
384impl From<DMA1RSEL_A> for u8 {
385 #[inline(always)]
386 fn from(variant: DMA1RSEL_A) -> Self {
387 variant as _
388 }
389}
390impl DMA1RSEL_R {
391 #[doc = "Get enumerated values variant"]
392 #[inline(always)]
393 pub fn variant(&self) -> DMA1RSEL_A {
394 match self.bits {
395 0 => DMA1RSEL_A::DATA1,
396 1 => DMA1RSEL_A::DDATA1,
397 2 => DMA1RSEL_A::QDATA1,
398 3 => DMA1RSEL_A::QDATA1BIG,
399 _ => unreachable!(),
400 }
401 }
402 #[doc = "Checks if the value of the field is `DATA1`"]
403 #[inline(always)]
404 pub fn is_data1(&self) -> bool {
405 *self == DMA1RSEL_A::DATA1
406 }
407 #[doc = "Checks if the value of the field is `DDATA1`"]
408 #[inline(always)]
409 pub fn is_ddata1(&self) -> bool {
410 *self == DMA1RSEL_A::DDATA1
411 }
412 #[doc = "Checks if the value of the field is `QDATA1`"]
413 #[inline(always)]
414 pub fn is_qdata1(&self) -> bool {
415 *self == DMA1RSEL_A::QDATA1
416 }
417 #[doc = "Checks if the value of the field is `QDATA1BIG`"]
418 #[inline(always)]
419 pub fn is_qdata1big(&self) -> bool {
420 *self == DMA1RSEL_A::QDATA1BIG
421 }
422}
423#[doc = "Field `DMA1RSEL` writer - DATA0 DMA Unaligned Read Register Select"]
424pub type DMA1RSEL_W<'a, const O: u8> =
425 crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, DMA1RSEL_A, 2, O>;
426impl<'a, const O: u8> DMA1RSEL_W<'a, O> {
427 #[doc = "`0`"]
428 #[inline(always)]
429 pub fn data1(self) -> &'a mut W {
430 self.variant(DMA1RSEL_A::DATA1)
431 }
432 #[doc = "`1`"]
433 #[inline(always)]
434 pub fn ddata1(self) -> &'a mut W {
435 self.variant(DMA1RSEL_A::DDATA1)
436 }
437 #[doc = "`10`"]
438 #[inline(always)]
439 pub fn qdata1(self) -> &'a mut W {
440 self.variant(DMA1RSEL_A::QDATA1)
441 }
442 #[doc = "`11`"]
443 #[inline(always)]
444 pub fn qdata1big(self) -> &'a mut W {
445 self.variant(DMA1RSEL_A::QDATA1BIG)
446 }
447}
448#[doc = "Field `COMBDMA0WEREQ` reader - Combined Data0 Write DMA Request"]
449pub type COMBDMA0WEREQ_R = crate::BitReader<bool>;
450#[doc = "Field `COMBDMA0WEREQ` writer - Combined Data0 Write DMA Request"]
451pub type COMBDMA0WEREQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
452impl R {
453 #[doc = "Bit 0 - AES Mode"]
454 #[inline(always)]
455 pub fn aes(&self) -> AES_R {
456 AES_R::new((self.bits & 1) != 0)
457 }
458 #[doc = "Bit 1 - Key Buffer Disable"]
459 #[inline(always)]
460 pub fn keybufdis(&self) -> KEYBUFDIS_R {
461 KEYBUFDIS_R::new(((self.bits >> 1) & 1) != 0)
462 }
463 #[doc = "Bit 2 - SHA Mode"]
464 #[inline(always)]
465 pub fn sha(&self) -> SHA_R {
466 SHA_R::new(((self.bits >> 2) & 1) != 0)
467 }
468 #[doc = "Bit 10 - No Stalling of Bus When Busy"]
469 #[inline(always)]
470 pub fn nobusystall(&self) -> NOBUSYSTALL_R {
471 NOBUSYSTALL_R::new(((self.bits >> 10) & 1) != 0)
472 }
473 #[doc = "Bits 14:15 - Increment Width"]
474 #[inline(always)]
475 pub fn incwidth(&self) -> INCWIDTH_R {
476 INCWIDTH_R::new(((self.bits >> 14) & 3) as u8)
477 }
478 #[doc = "Bits 16:17 - DMA0 Read Mode"]
479 #[inline(always)]
480 pub fn dma0mode(&self) -> DMA0MODE_R {
481 DMA0MODE_R::new(((self.bits >> 16) & 3) as u8)
482 }
483 #[doc = "Bits 20:21 - DMA0 Read Register Select"]
484 #[inline(always)]
485 pub fn dma0rsel(&self) -> DMA0RSEL_R {
486 DMA0RSEL_R::new(((self.bits >> 20) & 3) as u8)
487 }
488 #[doc = "Bits 24:25 - DMA1 Read Mode"]
489 #[inline(always)]
490 pub fn dma1mode(&self) -> DMA1MODE_R {
491 DMA1MODE_R::new(((self.bits >> 24) & 3) as u8)
492 }
493 #[doc = "Bits 28:29 - DATA0 DMA Unaligned Read Register Select"]
494 #[inline(always)]
495 pub fn dma1rsel(&self) -> DMA1RSEL_R {
496 DMA1RSEL_R::new(((self.bits >> 28) & 3) as u8)
497 }
498 #[doc = "Bit 31 - Combined Data0 Write DMA Request"]
499 #[inline(always)]
500 pub fn combdma0wereq(&self) -> COMBDMA0WEREQ_R {
501 COMBDMA0WEREQ_R::new(((self.bits >> 31) & 1) != 0)
502 }
503}
504impl W {
505 #[doc = "Bit 0 - AES Mode"]
506 #[inline(always)]
507 #[must_use]
508 pub fn aes(&mut self) -> AES_W<0> {
509 AES_W::new(self)
510 }
511 #[doc = "Bit 1 - Key Buffer Disable"]
512 #[inline(always)]
513 #[must_use]
514 pub fn keybufdis(&mut self) -> KEYBUFDIS_W<1> {
515 KEYBUFDIS_W::new(self)
516 }
517 #[doc = "Bit 2 - SHA Mode"]
518 #[inline(always)]
519 #[must_use]
520 pub fn sha(&mut self) -> SHA_W<2> {
521 SHA_W::new(self)
522 }
523 #[doc = "Bit 10 - No Stalling of Bus When Busy"]
524 #[inline(always)]
525 #[must_use]
526 pub fn nobusystall(&mut self) -> NOBUSYSTALL_W<10> {
527 NOBUSYSTALL_W::new(self)
528 }
529 #[doc = "Bits 14:15 - Increment Width"]
530 #[inline(always)]
531 #[must_use]
532 pub fn incwidth(&mut self) -> INCWIDTH_W<14> {
533 INCWIDTH_W::new(self)
534 }
535 #[doc = "Bits 16:17 - DMA0 Read Mode"]
536 #[inline(always)]
537 #[must_use]
538 pub fn dma0mode(&mut self) -> DMA0MODE_W<16> {
539 DMA0MODE_W::new(self)
540 }
541 #[doc = "Bits 20:21 - DMA0 Read Register Select"]
542 #[inline(always)]
543 #[must_use]
544 pub fn dma0rsel(&mut self) -> DMA0RSEL_W<20> {
545 DMA0RSEL_W::new(self)
546 }
547 #[doc = "Bits 24:25 - DMA1 Read Mode"]
548 #[inline(always)]
549 #[must_use]
550 pub fn dma1mode(&mut self) -> DMA1MODE_W<24> {
551 DMA1MODE_W::new(self)
552 }
553 #[doc = "Bits 28:29 - DATA0 DMA Unaligned Read Register Select"]
554 #[inline(always)]
555 #[must_use]
556 pub fn dma1rsel(&mut self) -> DMA1RSEL_W<28> {
557 DMA1RSEL_W::new(self)
558 }
559 #[doc = "Bit 31 - Combined Data0 Write DMA Request"]
560 #[inline(always)]
561 #[must_use]
562 pub fn combdma0wereq(&mut self) -> COMBDMA0WEREQ_W<31> {
563 COMBDMA0WEREQ_W::new(self)
564 }
565 #[doc = "Writes raw bits to the register."]
566 #[inline(always)]
567 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
568 self.0.bits(bits);
569 self
570 }
571}
572#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
573pub struct CTRL_SPEC;
574impl crate::RegisterSpec for CTRL_SPEC {
575 type Ux = u32;
576}
577#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
578impl crate::Readable for CTRL_SPEC {
579 type Reader = R;
580}
581#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
582impl crate::Writable for CTRL_SPEC {
583 type Writer = W;
584 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
585 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
586}
587#[doc = "`reset()` method sets CTRL to value 0"]
588impl crate::Resettable for CTRL_SPEC {
589 const RESET_VALUE: Self::Ux = 0;
590}