efm32tg11b_pac/efm32tg11b120/cmu/
oscencmd.rs

1#[doc = "Register `OSCENCMD` writer"]
2pub struct W(crate::W<OSCENCMD_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<OSCENCMD_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<OSCENCMD_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<OSCENCMD_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `HFRCOEN` writer - HFRCO Enable"]
23pub type HFRCOEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCENCMD_SPEC, bool, O>;
24#[doc = "Field `HFRCODIS` writer - HFRCO Disable"]
25pub type HFRCODIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCENCMD_SPEC, bool, O>;
26#[doc = "Field `HFXOEN` writer - HFXO Enable"]
27pub type HFXOEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCENCMD_SPEC, bool, O>;
28#[doc = "Field `HFXODIS` writer - HFXO Disable"]
29pub type HFXODIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCENCMD_SPEC, bool, O>;
30#[doc = "Field `AUXHFRCOEN` writer - AUXHFRCO Enable"]
31pub type AUXHFRCOEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCENCMD_SPEC, bool, O>;
32#[doc = "Field `AUXHFRCODIS` writer - AUXHFRCO Disable"]
33pub type AUXHFRCODIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCENCMD_SPEC, bool, O>;
34#[doc = "Field `LFRCOEN` writer - LFRCO Enable"]
35pub type LFRCOEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCENCMD_SPEC, bool, O>;
36#[doc = "Field `LFRCODIS` writer - LFRCO Disable"]
37pub type LFRCODIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCENCMD_SPEC, bool, O>;
38#[doc = "Field `LFXOEN` writer - LFXO Enable"]
39pub type LFXOEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCENCMD_SPEC, bool, O>;
40#[doc = "Field `LFXODIS` writer - LFXO Disable"]
41pub type LFXODIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCENCMD_SPEC, bool, O>;
42#[doc = "Field `DPLLEN` writer - DPLL Enable"]
43pub type DPLLEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCENCMD_SPEC, bool, O>;
44#[doc = "Field `DPLLDIS` writer - DPLL Disable"]
45pub type DPLLDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCENCMD_SPEC, bool, O>;
46impl W {
47    #[doc = "Bit 0 - HFRCO Enable"]
48    #[inline(always)]
49    #[must_use]
50    pub fn hfrcoen(&mut self) -> HFRCOEN_W<0> {
51        HFRCOEN_W::new(self)
52    }
53    #[doc = "Bit 1 - HFRCO Disable"]
54    #[inline(always)]
55    #[must_use]
56    pub fn hfrcodis(&mut self) -> HFRCODIS_W<1> {
57        HFRCODIS_W::new(self)
58    }
59    #[doc = "Bit 2 - HFXO Enable"]
60    #[inline(always)]
61    #[must_use]
62    pub fn hfxoen(&mut self) -> HFXOEN_W<2> {
63        HFXOEN_W::new(self)
64    }
65    #[doc = "Bit 3 - HFXO Disable"]
66    #[inline(always)]
67    #[must_use]
68    pub fn hfxodis(&mut self) -> HFXODIS_W<3> {
69        HFXODIS_W::new(self)
70    }
71    #[doc = "Bit 4 - AUXHFRCO Enable"]
72    #[inline(always)]
73    #[must_use]
74    pub fn auxhfrcoen(&mut self) -> AUXHFRCOEN_W<4> {
75        AUXHFRCOEN_W::new(self)
76    }
77    #[doc = "Bit 5 - AUXHFRCO Disable"]
78    #[inline(always)]
79    #[must_use]
80    pub fn auxhfrcodis(&mut self) -> AUXHFRCODIS_W<5> {
81        AUXHFRCODIS_W::new(self)
82    }
83    #[doc = "Bit 6 - LFRCO Enable"]
84    #[inline(always)]
85    #[must_use]
86    pub fn lfrcoen(&mut self) -> LFRCOEN_W<6> {
87        LFRCOEN_W::new(self)
88    }
89    #[doc = "Bit 7 - LFRCO Disable"]
90    #[inline(always)]
91    #[must_use]
92    pub fn lfrcodis(&mut self) -> LFRCODIS_W<7> {
93        LFRCODIS_W::new(self)
94    }
95    #[doc = "Bit 8 - LFXO Enable"]
96    #[inline(always)]
97    #[must_use]
98    pub fn lfxoen(&mut self) -> LFXOEN_W<8> {
99        LFXOEN_W::new(self)
100    }
101    #[doc = "Bit 9 - LFXO Disable"]
102    #[inline(always)]
103    #[must_use]
104    pub fn lfxodis(&mut self) -> LFXODIS_W<9> {
105        LFXODIS_W::new(self)
106    }
107    #[doc = "Bit 12 - DPLL Enable"]
108    #[inline(always)]
109    #[must_use]
110    pub fn dpllen(&mut self) -> DPLLEN_W<12> {
111        DPLLEN_W::new(self)
112    }
113    #[doc = "Bit 13 - DPLL Disable"]
114    #[inline(always)]
115    #[must_use]
116    pub fn dplldis(&mut self) -> DPLLDIS_W<13> {
117        DPLLDIS_W::new(self)
118    }
119    #[doc = "Writes raw bits to the register."]
120    #[inline(always)]
121    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
122        self.0.bits(bits);
123        self
124    }
125}
126#[doc = "Oscillator Enable/Disable Command Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [oscencmd](index.html) module"]
127pub struct OSCENCMD_SPEC;
128impl crate::RegisterSpec for OSCENCMD_SPEC {
129    type Ux = u32;
130}
131#[doc = "`write(|w| ..)` method takes [oscencmd::W](W) writer structure"]
132impl crate::Writable for OSCENCMD_SPEC {
133    type Writer = W;
134    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
135    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
136}
137#[doc = "`reset()` method sets OSCENCMD to value 0"]
138impl crate::Resettable for OSCENCMD_SPEC {
139    const RESET_VALUE: Self::Ux = 0;
140}
efm32tg11b_pac/efm32tg11b120/cmu/oscencmd.rs

efm32tg11b_pac/efm32tg11b120/cmu/
oscencmd.rs
