efm32tg11b_pac/efm32tg11b120/cmu/
adcctrl.rs

1#[doc = "Register `ADCCTRL` reader"]
2pub struct R(crate::R<ADCCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ADCCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ADCCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ADCCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ADCCTRL` writer"]
17pub struct W(crate::W<ADCCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ADCCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ADCCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ADCCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ADC0CLKDIV` reader - ADC0 Clock Prescaler"]
38pub type ADC0CLKDIV_R = crate::FieldReader<u8, ADC0CLKDIV_A>;
39#[doc = "ADC0 Clock Prescaler\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum ADC0CLKDIV_A {
43    #[doc = "0: `0`"]
44    NODIVISION = 0,
45}
46impl From<ADC0CLKDIV_A> for u8 {
47    #[inline(always)]
48    fn from(variant: ADC0CLKDIV_A) -> Self {
49        variant as _
50    }
51}
52impl ADC0CLKDIV_R {
53    #[doc = "Get enumerated values variant"]
54    #[inline(always)]
55    pub fn variant(&self) -> Option<ADC0CLKDIV_A> {
56        match self.bits {
57            0 => Some(ADC0CLKDIV_A::NODIVISION),
58            _ => None,
59        }
60    }
61    #[doc = "Checks if the value of the field is `NODIVISION`"]
62    #[inline(always)]
63    pub fn is_nodivision(&self) -> bool {
64        *self == ADC0CLKDIV_A::NODIVISION
65    }
66}
67#[doc = "Field `ADC0CLKDIV` writer - ADC0 Clock Prescaler"]
68pub type ADC0CLKDIV_W<'a, const O: u8> =
69    crate::FieldWriter<'a, u32, ADCCTRL_SPEC, u8, ADC0CLKDIV_A, 2, O>;
70impl<'a, const O: u8> ADC0CLKDIV_W<'a, O> {
71    #[doc = "`0`"]
72    #[inline(always)]
73    pub fn nodivision(self) -> &'a mut W {
74        self.variant(ADC0CLKDIV_A::NODIVISION)
75    }
76}
77#[doc = "Field `ADC0CLKSEL` reader - ADC0 Clock Select"]
78pub type ADC0CLKSEL_R = crate::FieldReader<u8, ADC0CLKSEL_A>;
79#[doc = "ADC0 Clock Select\n\nValue on reset: 0"]
80#[derive(Clone, Copy, Debug, PartialEq, Eq)]
81#[repr(u8)]
82pub enum ADC0CLKSEL_A {
83    #[doc = "0: ADC0 is not clocked"]
84    DISABLED = 0,
85    #[doc = "1: AUXHFRCO is clocking ADC0"]
86    AUXHFRCO = 1,
87    #[doc = "2: HFXO is clocking ADC0"]
88    HFXO = 2,
89    #[doc = "3: HFSRCCLK is clocking ADC0"]
90    HFSRCCLK = 3,
91}
92impl From<ADC0CLKSEL_A> for u8 {
93    #[inline(always)]
94    fn from(variant: ADC0CLKSEL_A) -> Self {
95        variant as _
96    }
97}
98impl ADC0CLKSEL_R {
99    #[doc = "Get enumerated values variant"]
100    #[inline(always)]
101    pub fn variant(&self) -> ADC0CLKSEL_A {
102        match self.bits {
103            0 => ADC0CLKSEL_A::DISABLED,
104            1 => ADC0CLKSEL_A::AUXHFRCO,
105            2 => ADC0CLKSEL_A::HFXO,
106            3 => ADC0CLKSEL_A::HFSRCCLK,
107            _ => unreachable!(),
108        }
109    }
110    #[doc = "Checks if the value of the field is `DISABLED`"]
111    #[inline(always)]
112    pub fn is_disabled(&self) -> bool {
113        *self == ADC0CLKSEL_A::DISABLED
114    }
115    #[doc = "Checks if the value of the field is `AUXHFRCO`"]
116    #[inline(always)]
117    pub fn is_auxhfrco(&self) -> bool {
118        *self == ADC0CLKSEL_A::AUXHFRCO
119    }
120    #[doc = "Checks if the value of the field is `HFXO`"]
121    #[inline(always)]
122    pub fn is_hfxo(&self) -> bool {
123        *self == ADC0CLKSEL_A::HFXO
124    }
125    #[doc = "Checks if the value of the field is `HFSRCCLK`"]
126    #[inline(always)]
127    pub fn is_hfsrcclk(&self) -> bool {
128        *self == ADC0CLKSEL_A::HFSRCCLK
129    }
130}
131#[doc = "Field `ADC0CLKSEL` writer - ADC0 Clock Select"]
132pub type ADC0CLKSEL_W<'a, const O: u8> =
133    crate::FieldWriterSafe<'a, u32, ADCCTRL_SPEC, u8, ADC0CLKSEL_A, 2, O>;
134impl<'a, const O: u8> ADC0CLKSEL_W<'a, O> {
135    #[doc = "ADC0 is not clocked"]
136    #[inline(always)]
137    pub fn disabled(self) -> &'a mut W {
138        self.variant(ADC0CLKSEL_A::DISABLED)
139    }
140    #[doc = "AUXHFRCO is clocking ADC0"]
141    #[inline(always)]
142    pub fn auxhfrco(self) -> &'a mut W {
143        self.variant(ADC0CLKSEL_A::AUXHFRCO)
144    }
145    #[doc = "HFXO is clocking ADC0"]
146    #[inline(always)]
147    pub fn hfxo(self) -> &'a mut W {
148        self.variant(ADC0CLKSEL_A::HFXO)
149    }
150    #[doc = "HFSRCCLK is clocking ADC0"]
151    #[inline(always)]
152    pub fn hfsrcclk(self) -> &'a mut W {
153        self.variant(ADC0CLKSEL_A::HFSRCCLK)
154    }
155}
156#[doc = "Field `ADC0CLKINV` reader - Invert Clock Selected By ADC0CLKSEL"]
157pub type ADC0CLKINV_R = crate::BitReader<bool>;
158#[doc = "Field `ADC0CLKINV` writer - Invert Clock Selected By ADC0CLKSEL"]
159pub type ADC0CLKINV_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCCTRL_SPEC, bool, O>;
160impl R {
161    #[doc = "Bits 0:1 - ADC0 Clock Prescaler"]
162    #[inline(always)]
163    pub fn adc0clkdiv(&self) -> ADC0CLKDIV_R {
164        ADC0CLKDIV_R::new((self.bits & 3) as u8)
165    }
166    #[doc = "Bits 4:5 - ADC0 Clock Select"]
167    #[inline(always)]
168    pub fn adc0clksel(&self) -> ADC0CLKSEL_R {
169        ADC0CLKSEL_R::new(((self.bits >> 4) & 3) as u8)
170    }
171    #[doc = "Bit 8 - Invert Clock Selected By ADC0CLKSEL"]
172    #[inline(always)]
173    pub fn adc0clkinv(&self) -> ADC0CLKINV_R {
174        ADC0CLKINV_R::new(((self.bits >> 8) & 1) != 0)
175    }
176}
177impl W {
178    #[doc = "Bits 0:1 - ADC0 Clock Prescaler"]
179    #[inline(always)]
180    #[must_use]
181    pub fn adc0clkdiv(&mut self) -> ADC0CLKDIV_W<0> {
182        ADC0CLKDIV_W::new(self)
183    }
184    #[doc = "Bits 4:5 - ADC0 Clock Select"]
185    #[inline(always)]
186    #[must_use]
187    pub fn adc0clksel(&mut self) -> ADC0CLKSEL_W<4> {
188        ADC0CLKSEL_W::new(self)
189    }
190    #[doc = "Bit 8 - Invert Clock Selected By ADC0CLKSEL"]
191    #[inline(always)]
192    #[must_use]
193    pub fn adc0clkinv(&mut self) -> ADC0CLKINV_W<8> {
194        ADC0CLKINV_W::new(self)
195    }
196    #[doc = "Writes raw bits to the register."]
197    #[inline(always)]
198    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
199        self.0.bits(bits);
200        self
201    }
202}
203#[doc = "ADC Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adcctrl](index.html) module"]
204pub struct ADCCTRL_SPEC;
205impl crate::RegisterSpec for ADCCTRL_SPEC {
206    type Ux = u32;
207}
208#[doc = "`read()` method returns [adcctrl::R](R) reader structure"]
209impl crate::Readable for ADCCTRL_SPEC {
210    type Reader = R;
211}
212#[doc = "`write(|w| ..)` method takes [adcctrl::W](W) writer structure"]
213impl crate::Writable for ADCCTRL_SPEC {
214    type Writer = W;
215    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
216    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
217}
218#[doc = "`reset()` method sets ADCCTRL to value 0"]
219impl crate::Resettable for ADCCTRL_SPEC {
220    const RESET_VALUE: Self::Ux = 0;
221}
efm32tg11b_pac/efm32tg11b120/cmu/adcctrl.rs

efm32tg11b_pac/efm32tg11b120/cmu/
adcctrl.rs
