efm32tg11b_pac/efm32tg11b120/adc0/
scanctrlx.rs

1#[doc = "Register `SCANCTRLX` reader"]
2pub struct R(crate::R<SCANCTRLX_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SCANCTRLX_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SCANCTRLX_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SCANCTRLX_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SCANCTRLX` writer"]
17pub struct W(crate::W<SCANCTRLX_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SCANCTRLX_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SCANCTRLX_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SCANCTRLX_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `VREFSEL` reader - Scan Channel Reference Selection"]
38pub type VREFSEL_R = crate::FieldReader<u8, VREFSEL_A>;
39#[doc = "Scan Channel Reference Selection\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum VREFSEL_A {
43    #[doc = "0: Internal 0.83V Bandgap reference"]
44    VBGR = 0,
45    #[doc = "1: Scaled AVDD: AVDD*(the VREF attenuation factor)"]
46    VDDXWATT = 1,
47    #[doc = "2: Scaled singled ended external Vref: ADCn_EXTP*(the VREF attenuation factor)"]
48    VREFPWATT = 2,
49    #[doc = "3: Raw single ended external Vref: ADCn_EXTP"]
50    VREFP = 3,
51    #[doc = "5: Scaled differential external Vref from : (ADCn_EXTP-ADCn_EXTN)*(the VREF attenuation factor)"]
52    VREFPNWATT = 5,
53    #[doc = "6: Raw differential external Vref from : (ADCn_EXTP-ADCn_EXTN)"]
54    VREFPN = 6,
55    #[doc = "7: Internal Bandgap reference at low setting 0.78V"]
56    VBGRLOW = 7,
57}
58impl From<VREFSEL_A> for u8 {
59    #[inline(always)]
60    fn from(variant: VREFSEL_A) -> Self {
61        variant as _
62    }
63}
64impl VREFSEL_R {
65    #[doc = "Get enumerated values variant"]
66    #[inline(always)]
67    pub fn variant(&self) -> Option<VREFSEL_A> {
68        match self.bits {
69            0 => Some(VREFSEL_A::VBGR),
70            1 => Some(VREFSEL_A::VDDXWATT),
71            2 => Some(VREFSEL_A::VREFPWATT),
72            3 => Some(VREFSEL_A::VREFP),
73            5 => Some(VREFSEL_A::VREFPNWATT),
74            6 => Some(VREFSEL_A::VREFPN),
75            7 => Some(VREFSEL_A::VBGRLOW),
76            _ => None,
77        }
78    }
79    #[doc = "Checks if the value of the field is `VBGR`"]
80    #[inline(always)]
81    pub fn is_vbgr(&self) -> bool {
82        *self == VREFSEL_A::VBGR
83    }
84    #[doc = "Checks if the value of the field is `VDDXWATT`"]
85    #[inline(always)]
86    pub fn is_vddxwatt(&self) -> bool {
87        *self == VREFSEL_A::VDDXWATT
88    }
89    #[doc = "Checks if the value of the field is `VREFPWATT`"]
90    #[inline(always)]
91    pub fn is_vrefpwatt(&self) -> bool {
92        *self == VREFSEL_A::VREFPWATT
93    }
94    #[doc = "Checks if the value of the field is `VREFP`"]
95    #[inline(always)]
96    pub fn is_vrefp(&self) -> bool {
97        *self == VREFSEL_A::VREFP
98    }
99    #[doc = "Checks if the value of the field is `VREFPNWATT`"]
100    #[inline(always)]
101    pub fn is_vrefpnwatt(&self) -> bool {
102        *self == VREFSEL_A::VREFPNWATT
103    }
104    #[doc = "Checks if the value of the field is `VREFPN`"]
105    #[inline(always)]
106    pub fn is_vrefpn(&self) -> bool {
107        *self == VREFSEL_A::VREFPN
108    }
109    #[doc = "Checks if the value of the field is `VBGRLOW`"]
110    #[inline(always)]
111    pub fn is_vbgrlow(&self) -> bool {
112        *self == VREFSEL_A::VBGRLOW
113    }
114}
115#[doc = "Field `VREFSEL` writer - Scan Channel Reference Selection"]
116pub type VREFSEL_W<'a, const O: u8> =
117    crate::FieldWriter<'a, u32, SCANCTRLX_SPEC, u8, VREFSEL_A, 3, O>;
118impl<'a, const O: u8> VREFSEL_W<'a, O> {
119    #[doc = "Internal 0.83V Bandgap reference"]
120    #[inline(always)]
121    pub fn vbgr(self) -> &'a mut W {
122        self.variant(VREFSEL_A::VBGR)
123    }
124    #[doc = "Scaled AVDD: AVDD*(the VREF attenuation factor)"]
125    #[inline(always)]
126    pub fn vddxwatt(self) -> &'a mut W {
127        self.variant(VREFSEL_A::VDDXWATT)
128    }
129    #[doc = "Scaled singled ended external Vref: ADCn_EXTP*(the VREF attenuation factor)"]
130    #[inline(always)]
131    pub fn vrefpwatt(self) -> &'a mut W {
132        self.variant(VREFSEL_A::VREFPWATT)
133    }
134    #[doc = "Raw single ended external Vref: ADCn_EXTP"]
135    #[inline(always)]
136    pub fn vrefp(self) -> &'a mut W {
137        self.variant(VREFSEL_A::VREFP)
138    }
139    #[doc = "Scaled differential external Vref from : (ADCn_EXTP-ADCn_EXTN)*(the VREF attenuation factor)"]
140    #[inline(always)]
141    pub fn vrefpnwatt(self) -> &'a mut W {
142        self.variant(VREFSEL_A::VREFPNWATT)
143    }
144    #[doc = "Raw differential external Vref from : (ADCn_EXTP-ADCn_EXTN)"]
145    #[inline(always)]
146    pub fn vrefpn(self) -> &'a mut W {
147        self.variant(VREFSEL_A::VREFPN)
148    }
149    #[doc = "Internal Bandgap reference at low setting 0.78V"]
150    #[inline(always)]
151    pub fn vbgrlow(self) -> &'a mut W {
152        self.variant(VREFSEL_A::VBGRLOW)
153    }
154}
155#[doc = "Field `VREFATTFIX` reader - Enable Fixed Scaling on VREF"]
156pub type VREFATTFIX_R = crate::BitReader<bool>;
157#[doc = "Field `VREFATTFIX` writer - Enable Fixed Scaling on VREF"]
158pub type VREFATTFIX_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCANCTRLX_SPEC, bool, O>;
159#[doc = "Field `VREFATT` reader - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
160pub type VREFATT_R = crate::FieldReader<u8, u8>;
161#[doc = "Field `VREFATT` writer - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
162pub type VREFATT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SCANCTRLX_SPEC, u8, u8, 4, O>;
163#[doc = "Field `VINATT` reader - Code for VIN Attenuation Factor"]
164pub type VINATT_R = crate::FieldReader<u8, u8>;
165#[doc = "Field `VINATT` writer - Code for VIN Attenuation Factor"]
166pub type VINATT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SCANCTRLX_SPEC, u8, u8, 4, O>;
167#[doc = "Field `DVL` reader - Scan DV Level Select"]
168pub type DVL_R = crate::FieldReader<u8, u8>;
169#[doc = "Field `DVL` writer - Scan DV Level Select"]
170pub type DVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SCANCTRLX_SPEC, u8, u8, 2, O>;
171#[doc = "Field `FIFOOFACT` reader - Scan FIFO Overflow Action"]
172pub type FIFOOFACT_R = crate::BitReader<bool>;
173#[doc = "Field `FIFOOFACT` writer - Scan FIFO Overflow Action"]
174pub type FIFOOFACT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCANCTRLX_SPEC, bool, O>;
175#[doc = "Field `PRSMODE` reader - Scan PRS Trigger Mode"]
176pub type PRSMODE_R = crate::BitReader<bool>;
177#[doc = "Field `PRSMODE` writer - Scan PRS Trigger Mode"]
178pub type PRSMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCANCTRLX_SPEC, bool, O>;
179#[doc = "Field `PRSSEL` reader - Scan Sequence PRS Trigger Select"]
180pub type PRSSEL_R = crate::FieldReader<u8, PRSSEL_A>;
181#[doc = "Scan Sequence PRS Trigger Select\n\nValue on reset: 0"]
182#[derive(Clone, Copy, Debug, PartialEq, Eq)]
183#[repr(u8)]
184pub enum PRSSEL_A {
185    #[doc = "0: PRS ch 0 triggers scan sequence"]
186    PRSCH0 = 0,
187    #[doc = "1: PRS ch 1 triggers scan sequence"]
188    PRSCH1 = 1,
189    #[doc = "2: PRS ch 2 triggers scan sequence"]
190    PRSCH2 = 2,
191    #[doc = "3: PRS ch 3 triggers scan sequence"]
192    PRSCH3 = 3,
193    #[doc = "4: PRS ch 4 triggers scan sequence"]
194    PRSCH4 = 4,
195    #[doc = "5: PRS ch 5 triggers scan sequence"]
196    PRSCH5 = 5,
197    #[doc = "6: PRS ch 6 triggers scan sequence"]
198    PRSCH6 = 6,
199    #[doc = "7: PRS ch 7 triggers scan sequence"]
200    PRSCH7 = 7,
201}
202impl From<PRSSEL_A> for u8 {
203    #[inline(always)]
204    fn from(variant: PRSSEL_A) -> Self {
205        variant as _
206    }
207}
208impl PRSSEL_R {
209    #[doc = "Get enumerated values variant"]
210    #[inline(always)]
211    pub fn variant(&self) -> PRSSEL_A {
212        match self.bits {
213            0 => PRSSEL_A::PRSCH0,
214            1 => PRSSEL_A::PRSCH1,
215            2 => PRSSEL_A::PRSCH2,
216            3 => PRSSEL_A::PRSCH3,
217            4 => PRSSEL_A::PRSCH4,
218            5 => PRSSEL_A::PRSCH5,
219            6 => PRSSEL_A::PRSCH6,
220            7 => PRSSEL_A::PRSCH7,
221            _ => unreachable!(),
222        }
223    }
224    #[doc = "Checks if the value of the field is `PRSCH0`"]
225    #[inline(always)]
226    pub fn is_prsch0(&self) -> bool {
227        *self == PRSSEL_A::PRSCH0
228    }
229    #[doc = "Checks if the value of the field is `PRSCH1`"]
230    #[inline(always)]
231    pub fn is_prsch1(&self) -> bool {
232        *self == PRSSEL_A::PRSCH1
233    }
234    #[doc = "Checks if the value of the field is `PRSCH2`"]
235    #[inline(always)]
236    pub fn is_prsch2(&self) -> bool {
237        *self == PRSSEL_A::PRSCH2
238    }
239    #[doc = "Checks if the value of the field is `PRSCH3`"]
240    #[inline(always)]
241    pub fn is_prsch3(&self) -> bool {
242        *self == PRSSEL_A::PRSCH3
243    }
244    #[doc = "Checks if the value of the field is `PRSCH4`"]
245    #[inline(always)]
246    pub fn is_prsch4(&self) -> bool {
247        *self == PRSSEL_A::PRSCH4
248    }
249    #[doc = "Checks if the value of the field is `PRSCH5`"]
250    #[inline(always)]
251    pub fn is_prsch5(&self) -> bool {
252        *self == PRSSEL_A::PRSCH5
253    }
254    #[doc = "Checks if the value of the field is `PRSCH6`"]
255    #[inline(always)]
256    pub fn is_prsch6(&self) -> bool {
257        *self == PRSSEL_A::PRSCH6
258    }
259    #[doc = "Checks if the value of the field is `PRSCH7`"]
260    #[inline(always)]
261    pub fn is_prsch7(&self) -> bool {
262        *self == PRSSEL_A::PRSCH7
263    }
264}
265#[doc = "Field `PRSSEL` writer - Scan Sequence PRS Trigger Select"]
266pub type PRSSEL_W<'a, const O: u8> =
267    crate::FieldWriterSafe<'a, u32, SCANCTRLX_SPEC, u8, PRSSEL_A, 3, O>;
268impl<'a, const O: u8> PRSSEL_W<'a, O> {
269    #[doc = "PRS ch 0 triggers scan sequence"]
270    #[inline(always)]
271    pub fn prsch0(self) -> &'a mut W {
272        self.variant(PRSSEL_A::PRSCH0)
273    }
274    #[doc = "PRS ch 1 triggers scan sequence"]
275    #[inline(always)]
276    pub fn prsch1(self) -> &'a mut W {
277        self.variant(PRSSEL_A::PRSCH1)
278    }
279    #[doc = "PRS ch 2 triggers scan sequence"]
280    #[inline(always)]
281    pub fn prsch2(self) -> &'a mut W {
282        self.variant(PRSSEL_A::PRSCH2)
283    }
284    #[doc = "PRS ch 3 triggers scan sequence"]
285    #[inline(always)]
286    pub fn prsch3(self) -> &'a mut W {
287        self.variant(PRSSEL_A::PRSCH3)
288    }
289    #[doc = "PRS ch 4 triggers scan sequence"]
290    #[inline(always)]
291    pub fn prsch4(self) -> &'a mut W {
292        self.variant(PRSSEL_A::PRSCH4)
293    }
294    #[doc = "PRS ch 5 triggers scan sequence"]
295    #[inline(always)]
296    pub fn prsch5(self) -> &'a mut W {
297        self.variant(PRSSEL_A::PRSCH5)
298    }
299    #[doc = "PRS ch 6 triggers scan sequence"]
300    #[inline(always)]
301    pub fn prsch6(self) -> &'a mut W {
302        self.variant(PRSSEL_A::PRSCH6)
303    }
304    #[doc = "PRS ch 7 triggers scan sequence"]
305    #[inline(always)]
306    pub fn prsch7(self) -> &'a mut W {
307        self.variant(PRSSEL_A::PRSCH7)
308    }
309}
310#[doc = "Field `CONVSTARTDELAY` reader - Delay Next Conversion Start If CONVSTARTDELAYEN is Set"]
311pub type CONVSTARTDELAY_R = crate::FieldReader<u8, u8>;
312#[doc = "Field `CONVSTARTDELAY` writer - Delay Next Conversion Start If CONVSTARTDELAYEN is Set"]
313pub type CONVSTARTDELAY_W<'a, const O: u8> =
314    crate::FieldWriter<'a, u32, SCANCTRLX_SPEC, u8, u8, 5, O>;
315#[doc = "Field `CONVSTARTDELAYEN` reader - Enable Delaying Next Conversion Start"]
316pub type CONVSTARTDELAYEN_R = crate::BitReader<bool>;
317#[doc = "Field `CONVSTARTDELAYEN` writer - Enable Delaying Next Conversion Start"]
318pub type CONVSTARTDELAYEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCANCTRLX_SPEC, bool, O>;
319#[doc = "Field `REPDELAY` reader - REPDELAY Select for SCAN REP Mode"]
320pub type REPDELAY_R = crate::FieldReader<u8, REPDELAY_A>;
321#[doc = "REPDELAY Select for SCAN REP Mode\n\nValue on reset: 0"]
322#[derive(Clone, Copy, Debug, PartialEq, Eq)]
323#[repr(u8)]
324pub enum REPDELAY_A {
325    #[doc = "0: No delay"]
326    NODELAY = 0,
327    #[doc = "1: 4 conversion clock cycles"]
328    _4CYCLES = 1,
329    #[doc = "2: 8 conversion clock cycles"]
330    _8CYCLES = 2,
331    #[doc = "3: 16 conversion clock cycles"]
332    _16CYCLES = 3,
333    #[doc = "4: 32 conversion clock cycles"]
334    _32CYCLES = 4,
335    #[doc = "5: 64 conversion clock cycles"]
336    _64CYCLES = 5,
337    #[doc = "6: 128 conversion clock cycles"]
338    _128CYCLES = 6,
339    #[doc = "7: 256 conversion clock cycles"]
340    _256CYCLES = 7,
341}
342impl From<REPDELAY_A> for u8 {
343    #[inline(always)]
344    fn from(variant: REPDELAY_A) -> Self {
345        variant as _
346    }
347}
348impl REPDELAY_R {
349    #[doc = "Get enumerated values variant"]
350    #[inline(always)]
351    pub fn variant(&self) -> REPDELAY_A {
352        match self.bits {
353            0 => REPDELAY_A::NODELAY,
354            1 => REPDELAY_A::_4CYCLES,
355            2 => REPDELAY_A::_8CYCLES,
356            3 => REPDELAY_A::_16CYCLES,
357            4 => REPDELAY_A::_32CYCLES,
358            5 => REPDELAY_A::_64CYCLES,
359            6 => REPDELAY_A::_128CYCLES,
360            7 => REPDELAY_A::_256CYCLES,
361            _ => unreachable!(),
362        }
363    }
364    #[doc = "Checks if the value of the field is `NODELAY`"]
365    #[inline(always)]
366    pub fn is_nodelay(&self) -> bool {
367        *self == REPDELAY_A::NODELAY
368    }
369    #[doc = "Checks if the value of the field is `_4CYCLES`"]
370    #[inline(always)]
371    pub fn is_4cycles(&self) -> bool {
372        *self == REPDELAY_A::_4CYCLES
373    }
374    #[doc = "Checks if the value of the field is `_8CYCLES`"]
375    #[inline(always)]
376    pub fn is_8cycles(&self) -> bool {
377        *self == REPDELAY_A::_8CYCLES
378    }
379    #[doc = "Checks if the value of the field is `_16CYCLES`"]
380    #[inline(always)]
381    pub fn is_16cycles(&self) -> bool {
382        *self == REPDELAY_A::_16CYCLES
383    }
384    #[doc = "Checks if the value of the field is `_32CYCLES`"]
385    #[inline(always)]
386    pub fn is_32cycles(&self) -> bool {
387        *self == REPDELAY_A::_32CYCLES
388    }
389    #[doc = "Checks if the value of the field is `_64CYCLES`"]
390    #[inline(always)]
391    pub fn is_64cycles(&self) -> bool {
392        *self == REPDELAY_A::_64CYCLES
393    }
394    #[doc = "Checks if the value of the field is `_128CYCLES`"]
395    #[inline(always)]
396    pub fn is_128cycles(&self) -> bool {
397        *self == REPDELAY_A::_128CYCLES
398    }
399    #[doc = "Checks if the value of the field is `_256CYCLES`"]
400    #[inline(always)]
401    pub fn is_256cycles(&self) -> bool {
402        *self == REPDELAY_A::_256CYCLES
403    }
404}
405#[doc = "Field `REPDELAY` writer - REPDELAY Select for SCAN REP Mode"]
406pub type REPDELAY_W<'a, const O: u8> =
407    crate::FieldWriterSafe<'a, u32, SCANCTRLX_SPEC, u8, REPDELAY_A, 3, O>;
408impl<'a, const O: u8> REPDELAY_W<'a, O> {
409    #[doc = "No delay"]
410    #[inline(always)]
411    pub fn nodelay(self) -> &'a mut W {
412        self.variant(REPDELAY_A::NODELAY)
413    }
414    #[doc = "4 conversion clock cycles"]
415    #[inline(always)]
416    pub fn _4cycles(self) -> &'a mut W {
417        self.variant(REPDELAY_A::_4CYCLES)
418    }
419    #[doc = "8 conversion clock cycles"]
420    #[inline(always)]
421    pub fn _8cycles(self) -> &'a mut W {
422        self.variant(REPDELAY_A::_8CYCLES)
423    }
424    #[doc = "16 conversion clock cycles"]
425    #[inline(always)]
426    pub fn _16cycles(self) -> &'a mut W {
427        self.variant(REPDELAY_A::_16CYCLES)
428    }
429    #[doc = "32 conversion clock cycles"]
430    #[inline(always)]
431    pub fn _32cycles(self) -> &'a mut W {
432        self.variant(REPDELAY_A::_32CYCLES)
433    }
434    #[doc = "64 conversion clock cycles"]
435    #[inline(always)]
436    pub fn _64cycles(self) -> &'a mut W {
437        self.variant(REPDELAY_A::_64CYCLES)
438    }
439    #[doc = "128 conversion clock cycles"]
440    #[inline(always)]
441    pub fn _128cycles(self) -> &'a mut W {
442        self.variant(REPDELAY_A::_128CYCLES)
443    }
444    #[doc = "256 conversion clock cycles"]
445    #[inline(always)]
446    pub fn _256cycles(self) -> &'a mut W {
447        self.variant(REPDELAY_A::_256CYCLES)
448    }
449}
450impl R {
451    #[doc = "Bits 0:2 - Scan Channel Reference Selection"]
452    #[inline(always)]
453    pub fn vrefsel(&self) -> VREFSEL_R {
454        VREFSEL_R::new((self.bits & 7) as u8)
455    }
456    #[doc = "Bit 3 - Enable Fixed Scaling on VREF"]
457    #[inline(always)]
458    pub fn vrefattfix(&self) -> VREFATTFIX_R {
459        VREFATTFIX_R::new(((self.bits >> 3) & 1) != 0)
460    }
461    #[doc = "Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
462    #[inline(always)]
463    pub fn vrefatt(&self) -> VREFATT_R {
464        VREFATT_R::new(((self.bits >> 4) & 0x0f) as u8)
465    }
466    #[doc = "Bits 8:11 - Code for VIN Attenuation Factor"]
467    #[inline(always)]
468    pub fn vinatt(&self) -> VINATT_R {
469        VINATT_R::new(((self.bits >> 8) & 0x0f) as u8)
470    }
471    #[doc = "Bits 12:13 - Scan DV Level Select"]
472    #[inline(always)]
473    pub fn dvl(&self) -> DVL_R {
474        DVL_R::new(((self.bits >> 12) & 3) as u8)
475    }
476    #[doc = "Bit 14 - Scan FIFO Overflow Action"]
477    #[inline(always)]
478    pub fn fifoofact(&self) -> FIFOOFACT_R {
479        FIFOOFACT_R::new(((self.bits >> 14) & 1) != 0)
480    }
481    #[doc = "Bit 16 - Scan PRS Trigger Mode"]
482    #[inline(always)]
483    pub fn prsmode(&self) -> PRSMODE_R {
484        PRSMODE_R::new(((self.bits >> 16) & 1) != 0)
485    }
486    #[doc = "Bits 17:19 - Scan Sequence PRS Trigger Select"]
487    #[inline(always)]
488    pub fn prssel(&self) -> PRSSEL_R {
489        PRSSEL_R::new(((self.bits >> 17) & 7) as u8)
490    }
491    #[doc = "Bits 22:26 - Delay Next Conversion Start If CONVSTARTDELAYEN is Set"]
492    #[inline(always)]
493    pub fn convstartdelay(&self) -> CONVSTARTDELAY_R {
494        CONVSTARTDELAY_R::new(((self.bits >> 22) & 0x1f) as u8)
495    }
496    #[doc = "Bit 27 - Enable Delaying Next Conversion Start"]
497    #[inline(always)]
498    pub fn convstartdelayen(&self) -> CONVSTARTDELAYEN_R {
499        CONVSTARTDELAYEN_R::new(((self.bits >> 27) & 1) != 0)
500    }
501    #[doc = "Bits 29:31 - REPDELAY Select for SCAN REP Mode"]
502    #[inline(always)]
503    pub fn repdelay(&self) -> REPDELAY_R {
504        REPDELAY_R::new(((self.bits >> 29) & 7) as u8)
505    }
506}
507impl W {
508    #[doc = "Bits 0:2 - Scan Channel Reference Selection"]
509    #[inline(always)]
510    #[must_use]
511    pub fn vrefsel(&mut self) -> VREFSEL_W<0> {
512        VREFSEL_W::new(self)
513    }
514    #[doc = "Bit 3 - Enable Fixed Scaling on VREF"]
515    #[inline(always)]
516    #[must_use]
517    pub fn vrefattfix(&mut self) -> VREFATTFIX_W<3> {
518        VREFATTFIX_W::new(self)
519    }
520    #[doc = "Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
521    #[inline(always)]
522    #[must_use]
523    pub fn vrefatt(&mut self) -> VREFATT_W<4> {
524        VREFATT_W::new(self)
525    }
526    #[doc = "Bits 8:11 - Code for VIN Attenuation Factor"]
527    #[inline(always)]
528    #[must_use]
529    pub fn vinatt(&mut self) -> VINATT_W<8> {
530        VINATT_W::new(self)
531    }
532    #[doc = "Bits 12:13 - Scan DV Level Select"]
533    #[inline(always)]
534    #[must_use]
535    pub fn dvl(&mut self) -> DVL_W<12> {
536        DVL_W::new(self)
537    }
538    #[doc = "Bit 14 - Scan FIFO Overflow Action"]
539    #[inline(always)]
540    #[must_use]
541    pub fn fifoofact(&mut self) -> FIFOOFACT_W<14> {
542        FIFOOFACT_W::new(self)
543    }
544    #[doc = "Bit 16 - Scan PRS Trigger Mode"]
545    #[inline(always)]
546    #[must_use]
547    pub fn prsmode(&mut self) -> PRSMODE_W<16> {
548        PRSMODE_W::new(self)
549    }
550    #[doc = "Bits 17:19 - Scan Sequence PRS Trigger Select"]
551    #[inline(always)]
552    #[must_use]
553    pub fn prssel(&mut self) -> PRSSEL_W<17> {
554        PRSSEL_W::new(self)
555    }
556    #[doc = "Bits 22:26 - Delay Next Conversion Start If CONVSTARTDELAYEN is Set"]
557    #[inline(always)]
558    #[must_use]
559    pub fn convstartdelay(&mut self) -> CONVSTARTDELAY_W<22> {
560        CONVSTARTDELAY_W::new(self)
561    }
562    #[doc = "Bit 27 - Enable Delaying Next Conversion Start"]
563    #[inline(always)]
564    #[must_use]
565    pub fn convstartdelayen(&mut self) -> CONVSTARTDELAYEN_W<27> {
566        CONVSTARTDELAYEN_W::new(self)
567    }
568    #[doc = "Bits 29:31 - REPDELAY Select for SCAN REP Mode"]
569    #[inline(always)]
570    #[must_use]
571    pub fn repdelay(&mut self) -> REPDELAY_W<29> {
572        REPDELAY_W::new(self)
573    }
574    #[doc = "Writes raw bits to the register."]
575    #[inline(always)]
576    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
577        self.0.bits(bits);
578        self
579    }
580}
581#[doc = "Scan Control Register Continued\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scanctrlx](index.html) module"]
582pub struct SCANCTRLX_SPEC;
583impl crate::RegisterSpec for SCANCTRLX_SPEC {
584    type Ux = u32;
585}
586#[doc = "`read()` method returns [scanctrlx::R](R) reader structure"]
587impl crate::Readable for SCANCTRLX_SPEC {
588    type Reader = R;
589}
590#[doc = "`write(|w| ..)` method takes [scanctrlx::W](W) writer structure"]
591impl crate::Writable for SCANCTRLX_SPEC {
592    type Writer = W;
593    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
594    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
595}
596#[doc = "`reset()` method sets SCANCTRLX to value 0"]
597impl crate::Resettable for SCANCTRLX_SPEC {
598    const RESET_VALUE: Self::Ux = 0;
599}
efm32tg11b_pac/efm32tg11b120/adc0/scanctrlx.rs

efm32tg11b_pac/efm32tg11b120/adc0/
scanctrlx.rs
