efm32tg11b_pac/efm32tg11b540/vdac0/
opa1_timer.rs

1#[doc = "Register `OPA1_TIMER` reader"]
2pub struct R(crate::R<OPA1_TIMER_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<OPA1_TIMER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<OPA1_TIMER_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<OPA1_TIMER_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `OPA1_TIMER` writer"]
17pub struct W(crate::W<OPA1_TIMER_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<OPA1_TIMER_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<OPA1_TIMER_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<OPA1_TIMER_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `STARTUPDLY` reader - OPAx Startup Delay Count Value"]
38pub type STARTUPDLY_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `STARTUPDLY` writer - OPAx Startup Delay Count Value"]
40pub type STARTUPDLY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OPA1_TIMER_SPEC, u8, u8, 6, O>;
41#[doc = "Field `WARMUPTIME` reader - OPAx Warmup Time Count Value"]
42pub type WARMUPTIME_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `WARMUPTIME` writer - OPAx Warmup Time Count Value"]
44pub type WARMUPTIME_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OPA1_TIMER_SPEC, u8, u8, 7, O>;
45#[doc = "Field `SETTLETIME` reader - OPAx Output Settling Timeout Value"]
46pub type SETTLETIME_R = crate::FieldReader<u16, u16>;
47#[doc = "Field `SETTLETIME` writer - OPAx Output Settling Timeout Value"]
48pub type SETTLETIME_W<'a, const O: u8> =
49    crate::FieldWriter<'a, u32, OPA1_TIMER_SPEC, u16, u16, 10, O>;
50impl R {
51    #[doc = "Bits 0:5 - OPAx Startup Delay Count Value"]
52    #[inline(always)]
53    pub fn startupdly(&self) -> STARTUPDLY_R {
54        STARTUPDLY_R::new((self.bits & 0x3f) as u8)
55    }
56    #[doc = "Bits 8:14 - OPAx Warmup Time Count Value"]
57    #[inline(always)]
58    pub fn warmuptime(&self) -> WARMUPTIME_R {
59        WARMUPTIME_R::new(((self.bits >> 8) & 0x7f) as u8)
60    }
61    #[doc = "Bits 16:25 - OPAx Output Settling Timeout Value"]
62    #[inline(always)]
63    pub fn settletime(&self) -> SETTLETIME_R {
64        SETTLETIME_R::new(((self.bits >> 16) & 0x03ff) as u16)
65    }
66}
67impl W {
68    #[doc = "Bits 0:5 - OPAx Startup Delay Count Value"]
69    #[inline(always)]
70    #[must_use]
71    pub fn startupdly(&mut self) -> STARTUPDLY_W<0> {
72        STARTUPDLY_W::new(self)
73    }
74    #[doc = "Bits 8:14 - OPAx Warmup Time Count Value"]
75    #[inline(always)]
76    #[must_use]
77    pub fn warmuptime(&mut self) -> WARMUPTIME_W<8> {
78        WARMUPTIME_W::new(self)
79    }
80    #[doc = "Bits 16:25 - OPAx Output Settling Timeout Value"]
81    #[inline(always)]
82    #[must_use]
83    pub fn settletime(&mut self) -> SETTLETIME_W<16> {
84        SETTLETIME_W::new(self)
85    }
86    #[doc = "Writes raw bits to the register."]
87    #[inline(always)]
88    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
89        self.0.bits(bits);
90        self
91    }
92}
93#[doc = "Operational Amplifier Timer Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opa1_timer](index.html) module"]
94pub struct OPA1_TIMER_SPEC;
95impl crate::RegisterSpec for OPA1_TIMER_SPEC {
96    type Ux = u32;
97}
98#[doc = "`read()` method returns [opa1_timer::R](R) reader structure"]
99impl crate::Readable for OPA1_TIMER_SPEC {
100    type Reader = R;
101}
102#[doc = "`write(|w| ..)` method takes [opa1_timer::W](W) writer structure"]
103impl crate::Writable for OPA1_TIMER_SPEC {
104    type Writer = W;
105    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
106    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
107}
108#[doc = "`reset()` method sets OPA1_TIMER to value 0x0001_0700"]
109impl crate::Resettable for OPA1_TIMER_SPEC {
110    const RESET_VALUE: Self::Ux = 0x0001_0700;
111}
efm32tg11b_pac/efm32tg11b540/vdac0/opa1_timer.rs

efm32tg11b_pac/efm32tg11b540/vdac0/
opa1_timer.rs
