1#[doc = "Register `PPUPATD0` reader"]
2pub struct R(crate::R<PPUPATD0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<PPUPATD0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<PPUPATD0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<PPUPATD0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `PPUPATD0` writer"]
17pub struct W(crate::W<PPUPATD0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<PPUPATD0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<PPUPATD0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<PPUPATD0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `ACMP0` reader - Analog Comparator 0 access control bit"]
38pub type ACMP0_R = crate::BitReader<bool>;
39#[doc = "Field `ACMP0` writer - Analog Comparator 0 access control bit"]
40pub type ACMP0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
41#[doc = "Field `ACMP1` reader - Analog Comparator 1 access control bit"]
42pub type ACMP1_R = crate::BitReader<bool>;
43#[doc = "Field `ACMP1` writer - Analog Comparator 1 access control bit"]
44pub type ACMP1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
45#[doc = "Field `ADC0` reader - Analog to Digital Converter 0 access control bit"]
46pub type ADC0_R = crate::BitReader<bool>;
47#[doc = "Field `ADC0` writer - Analog to Digital Converter 0 access control bit"]
48pub type ADC0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
49#[doc = "Field `CAN0` reader - CAN 0 access control bit"]
50pub type CAN0_R = crate::BitReader<bool>;
51#[doc = "Field `CAN0` writer - CAN 0 access control bit"]
52pub type CAN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
53#[doc = "Field `CMU` reader - Clock Management Unit access control bit"]
54pub type CMU_R = crate::BitReader<bool>;
55#[doc = "Field `CMU` writer - Clock Management Unit access control bit"]
56pub type CMU_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
57#[doc = "Field `CRYOTIMER` reader - CRYOTIMER access control bit"]
58pub type CRYOTIMER_R = crate::BitReader<bool>;
59#[doc = "Field `CRYOTIMER` writer - CRYOTIMER access control bit"]
60pub type CRYOTIMER_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
61#[doc = "Field `CRYPTO0` reader - Advanced Encryption Standard Accelerator access control bit"]
62pub type CRYPTO0_R = crate::BitReader<bool>;
63#[doc = "Field `CRYPTO0` writer - Advanced Encryption Standard Accelerator access control bit"]
64pub type CRYPTO0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
65#[doc = "Field `CSEN` reader - Capacitive touch sense module access control bit"]
66pub type CSEN_R = crate::BitReader<bool>;
67#[doc = "Field `CSEN` writer - Capacitive touch sense module access control bit"]
68pub type CSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
69#[doc = "Field `VDAC0` reader - Digital to Analog Converter 0 access control bit"]
70pub type VDAC0_R = crate::BitReader<bool>;
71#[doc = "Field `VDAC0` writer - Digital to Analog Converter 0 access control bit"]
72pub type VDAC0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
73#[doc = "Field `PRS` reader - Peripheral Reflex System access control bit"]
74pub type PRS_R = crate::BitReader<bool>;
75#[doc = "Field `PRS` writer - Peripheral Reflex System access control bit"]
76pub type PRS_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
77#[doc = "Field `EMU` reader - Energy Management Unit access control bit"]
78pub type EMU_R = crate::BitReader<bool>;
79#[doc = "Field `EMU` writer - Energy Management Unit access control bit"]
80pub type EMU_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
81#[doc = "Field `GPCRC` reader - General Purpose CRC access control bit"]
82pub type GPCRC_R = crate::BitReader<bool>;
83#[doc = "Field `GPCRC` writer - General Purpose CRC access control bit"]
84pub type GPCRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
85#[doc = "Field `GPIO` reader - General purpose Input/Output access control bit"]
86pub type GPIO_R = crate::BitReader<bool>;
87#[doc = "Field `GPIO` writer - General purpose Input/Output access control bit"]
88pub type GPIO_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
89#[doc = "Field `I2C0` reader - I2C 0 access control bit"]
90pub type I2C0_R = crate::BitReader<bool>;
91#[doc = "Field `I2C0` writer - I2C 0 access control bit"]
92pub type I2C0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
93#[doc = "Field `I2C1` reader - I2C 1 access control bit"]
94pub type I2C1_R = crate::BitReader<bool>;
95#[doc = "Field `I2C1` writer - I2C 1 access control bit"]
96pub type I2C1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
97#[doc = "Field `MSC` reader - Memory System Controller access control bit"]
98pub type MSC_R = crate::BitReader<bool>;
99#[doc = "Field `MSC` writer - Memory System Controller access control bit"]
100pub type MSC_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
101#[doc = "Field `LDMA` reader - Linked Direct Memory Access Controller access control bit"]
102pub type LDMA_R = crate::BitReader<bool>;
103#[doc = "Field `LDMA` writer - Linked Direct Memory Access Controller access control bit"]
104pub type LDMA_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
105#[doc = "Field `LESENSE` reader - Low Energy Sensor Interface access control bit"]
106pub type LESENSE_R = crate::BitReader<bool>;
107#[doc = "Field `LESENSE` writer - Low Energy Sensor Interface access control bit"]
108pub type LESENSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
109#[doc = "Field `LETIMER0` reader - Low Energy Timer 0 access control bit"]
110pub type LETIMER0_R = crate::BitReader<bool>;
111#[doc = "Field `LETIMER0` writer - Low Energy Timer 0 access control bit"]
112pub type LETIMER0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
113#[doc = "Field `LEUART0` reader - Low Energy UART 0 access control bit"]
114pub type LEUART0_R = crate::BitReader<bool>;
115#[doc = "Field `LEUART0` writer - Low Energy UART 0 access control bit"]
116pub type LEUART0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
117#[doc = "Field `PCNT0` reader - Pulse Counter 0 access control bit"]
118pub type PCNT0_R = crate::BitReader<bool>;
119#[doc = "Field `PCNT0` writer - Pulse Counter 0 access control bit"]
120pub type PCNT0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
121#[doc = "Field `RMU` reader - Reset Management Unit access control bit"]
122pub type RMU_R = crate::BitReader<bool>;
123#[doc = "Field `RMU` writer - Reset Management Unit access control bit"]
124pub type RMU_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
125#[doc = "Field `RTCC` reader - Real-Time Counter and Calendar access control bit"]
126pub type RTCC_R = crate::BitReader<bool>;
127#[doc = "Field `RTCC` writer - Real-Time Counter and Calendar access control bit"]
128pub type RTCC_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
129#[doc = "Field `SMU` reader - Security Management Unit access control bit"]
130pub type SMU_R = crate::BitReader<bool>;
131#[doc = "Field `SMU` writer - Security Management Unit access control bit"]
132pub type SMU_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
133#[doc = "Field `TIMER0` reader - Timer 0 access control bit"]
134pub type TIMER0_R = crate::BitReader<bool>;
135#[doc = "Field `TIMER0` writer - Timer 0 access control bit"]
136pub type TIMER0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
137#[doc = "Field `TIMER1` reader - Timer 1 access control bit"]
138pub type TIMER1_R = crate::BitReader<bool>;
139#[doc = "Field `TIMER1` writer - Timer 1 access control bit"]
140pub type TIMER1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
141#[doc = "Field `TRNG0` reader - True Random Number Generator 0 access control bit"]
142pub type TRNG0_R = crate::BitReader<bool>;
143#[doc = "Field `TRNG0` writer - True Random Number Generator 0 access control bit"]
144pub type TRNG0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
145#[doc = "Field `UART0` reader - Universal Asynchronous Receiver/Transmitter 0 access control bit"]
146pub type UART0_R = crate::BitReader<bool>;
147#[doc = "Field `UART0` writer - Universal Asynchronous Receiver/Transmitter 0 access control bit"]
148pub type UART0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
149#[doc = "Field `USART0` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
150pub type USART0_R = crate::BitReader<bool>;
151#[doc = "Field `USART0` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
152pub type USART0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
153#[doc = "Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
154pub type USART1_R = crate::BitReader<bool>;
155#[doc = "Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
156pub type USART1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
157#[doc = "Field `USART2` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
158pub type USART2_R = crate::BitReader<bool>;
159#[doc = "Field `USART2` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
160pub type USART2_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, O>;
161impl R {
162 #[doc = "Bit 0 - Analog Comparator 0 access control bit"]
163 #[inline(always)]
164 pub fn acmp0(&self) -> ACMP0_R {
165 ACMP0_R::new((self.bits & 1) != 0)
166 }
167 #[doc = "Bit 1 - Analog Comparator 1 access control bit"]
168 #[inline(always)]
169 pub fn acmp1(&self) -> ACMP1_R {
170 ACMP1_R::new(((self.bits >> 1) & 1) != 0)
171 }
172 #[doc = "Bit 2 - Analog to Digital Converter 0 access control bit"]
173 #[inline(always)]
174 pub fn adc0(&self) -> ADC0_R {
175 ADC0_R::new(((self.bits >> 2) & 1) != 0)
176 }
177 #[doc = "Bit 3 - CAN 0 access control bit"]
178 #[inline(always)]
179 pub fn can0(&self) -> CAN0_R {
180 CAN0_R::new(((self.bits >> 3) & 1) != 0)
181 }
182 #[doc = "Bit 4 - Clock Management Unit access control bit"]
183 #[inline(always)]
184 pub fn cmu(&self) -> CMU_R {
185 CMU_R::new(((self.bits >> 4) & 1) != 0)
186 }
187 #[doc = "Bit 5 - CRYOTIMER access control bit"]
188 #[inline(always)]
189 pub fn cryotimer(&self) -> CRYOTIMER_R {
190 CRYOTIMER_R::new(((self.bits >> 5) & 1) != 0)
191 }
192 #[doc = "Bit 6 - Advanced Encryption Standard Accelerator access control bit"]
193 #[inline(always)]
194 pub fn crypto0(&self) -> CRYPTO0_R {
195 CRYPTO0_R::new(((self.bits >> 6) & 1) != 0)
196 }
197 #[doc = "Bit 7 - Capacitive touch sense module access control bit"]
198 #[inline(always)]
199 pub fn csen(&self) -> CSEN_R {
200 CSEN_R::new(((self.bits >> 7) & 1) != 0)
201 }
202 #[doc = "Bit 8 - Digital to Analog Converter 0 access control bit"]
203 #[inline(always)]
204 pub fn vdac0(&self) -> VDAC0_R {
205 VDAC0_R::new(((self.bits >> 8) & 1) != 0)
206 }
207 #[doc = "Bit 9 - Peripheral Reflex System access control bit"]
208 #[inline(always)]
209 pub fn prs(&self) -> PRS_R {
210 PRS_R::new(((self.bits >> 9) & 1) != 0)
211 }
212 #[doc = "Bit 10 - Energy Management Unit access control bit"]
213 #[inline(always)]
214 pub fn emu(&self) -> EMU_R {
215 EMU_R::new(((self.bits >> 10) & 1) != 0)
216 }
217 #[doc = "Bit 11 - General Purpose CRC access control bit"]
218 #[inline(always)]
219 pub fn gpcrc(&self) -> GPCRC_R {
220 GPCRC_R::new(((self.bits >> 11) & 1) != 0)
221 }
222 #[doc = "Bit 12 - General purpose Input/Output access control bit"]
223 #[inline(always)]
224 pub fn gpio(&self) -> GPIO_R {
225 GPIO_R::new(((self.bits >> 12) & 1) != 0)
226 }
227 #[doc = "Bit 13 - I2C 0 access control bit"]
228 #[inline(always)]
229 pub fn i2c0(&self) -> I2C0_R {
230 I2C0_R::new(((self.bits >> 13) & 1) != 0)
231 }
232 #[doc = "Bit 14 - I2C 1 access control bit"]
233 #[inline(always)]
234 pub fn i2c1(&self) -> I2C1_R {
235 I2C1_R::new(((self.bits >> 14) & 1) != 0)
236 }
237 #[doc = "Bit 15 - Memory System Controller access control bit"]
238 #[inline(always)]
239 pub fn msc(&self) -> MSC_R {
240 MSC_R::new(((self.bits >> 15) & 1) != 0)
241 }
242 #[doc = "Bit 17 - Linked Direct Memory Access Controller access control bit"]
243 #[inline(always)]
244 pub fn ldma(&self) -> LDMA_R {
245 LDMA_R::new(((self.bits >> 17) & 1) != 0)
246 }
247 #[doc = "Bit 18 - Low Energy Sensor Interface access control bit"]
248 #[inline(always)]
249 pub fn lesense(&self) -> LESENSE_R {
250 LESENSE_R::new(((self.bits >> 18) & 1) != 0)
251 }
252 #[doc = "Bit 19 - Low Energy Timer 0 access control bit"]
253 #[inline(always)]
254 pub fn letimer0(&self) -> LETIMER0_R {
255 LETIMER0_R::new(((self.bits >> 19) & 1) != 0)
256 }
257 #[doc = "Bit 20 - Low Energy UART 0 access control bit"]
258 #[inline(always)]
259 pub fn leuart0(&self) -> LEUART0_R {
260 LEUART0_R::new(((self.bits >> 20) & 1) != 0)
261 }
262 #[doc = "Bit 21 - Pulse Counter 0 access control bit"]
263 #[inline(always)]
264 pub fn pcnt0(&self) -> PCNT0_R {
265 PCNT0_R::new(((self.bits >> 21) & 1) != 0)
266 }
267 #[doc = "Bit 22 - Reset Management Unit access control bit"]
268 #[inline(always)]
269 pub fn rmu(&self) -> RMU_R {
270 RMU_R::new(((self.bits >> 22) & 1) != 0)
271 }
272 #[doc = "Bit 23 - Real-Time Counter and Calendar access control bit"]
273 #[inline(always)]
274 pub fn rtcc(&self) -> RTCC_R {
275 RTCC_R::new(((self.bits >> 23) & 1) != 0)
276 }
277 #[doc = "Bit 24 - Security Management Unit access control bit"]
278 #[inline(always)]
279 pub fn smu(&self) -> SMU_R {
280 SMU_R::new(((self.bits >> 24) & 1) != 0)
281 }
282 #[doc = "Bit 25 - Timer 0 access control bit"]
283 #[inline(always)]
284 pub fn timer0(&self) -> TIMER0_R {
285 TIMER0_R::new(((self.bits >> 25) & 1) != 0)
286 }
287 #[doc = "Bit 26 - Timer 1 access control bit"]
288 #[inline(always)]
289 pub fn timer1(&self) -> TIMER1_R {
290 TIMER1_R::new(((self.bits >> 26) & 1) != 0)
291 }
292 #[doc = "Bit 27 - True Random Number Generator 0 access control bit"]
293 #[inline(always)]
294 pub fn trng0(&self) -> TRNG0_R {
295 TRNG0_R::new(((self.bits >> 27) & 1) != 0)
296 }
297 #[doc = "Bit 28 - Universal Asynchronous Receiver/Transmitter 0 access control bit"]
298 #[inline(always)]
299 pub fn uart0(&self) -> UART0_R {
300 UART0_R::new(((self.bits >> 28) & 1) != 0)
301 }
302 #[doc = "Bit 29 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
303 #[inline(always)]
304 pub fn usart0(&self) -> USART0_R {
305 USART0_R::new(((self.bits >> 29) & 1) != 0)
306 }
307 #[doc = "Bit 30 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
308 #[inline(always)]
309 pub fn usart1(&self) -> USART1_R {
310 USART1_R::new(((self.bits >> 30) & 1) != 0)
311 }
312 #[doc = "Bit 31 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
313 #[inline(always)]
314 pub fn usart2(&self) -> USART2_R {
315 USART2_R::new(((self.bits >> 31) & 1) != 0)
316 }
317}
318impl W {
319 #[doc = "Bit 0 - Analog Comparator 0 access control bit"]
320 #[inline(always)]
321 #[must_use]
322 pub fn acmp0(&mut self) -> ACMP0_W<0> {
323 ACMP0_W::new(self)
324 }
325 #[doc = "Bit 1 - Analog Comparator 1 access control bit"]
326 #[inline(always)]
327 #[must_use]
328 pub fn acmp1(&mut self) -> ACMP1_W<1> {
329 ACMP1_W::new(self)
330 }
331 #[doc = "Bit 2 - Analog to Digital Converter 0 access control bit"]
332 #[inline(always)]
333 #[must_use]
334 pub fn adc0(&mut self) -> ADC0_W<2> {
335 ADC0_W::new(self)
336 }
337 #[doc = "Bit 3 - CAN 0 access control bit"]
338 #[inline(always)]
339 #[must_use]
340 pub fn can0(&mut self) -> CAN0_W<3> {
341 CAN0_W::new(self)
342 }
343 #[doc = "Bit 4 - Clock Management Unit access control bit"]
344 #[inline(always)]
345 #[must_use]
346 pub fn cmu(&mut self) -> CMU_W<4> {
347 CMU_W::new(self)
348 }
349 #[doc = "Bit 5 - CRYOTIMER access control bit"]
350 #[inline(always)]
351 #[must_use]
352 pub fn cryotimer(&mut self) -> CRYOTIMER_W<5> {
353 CRYOTIMER_W::new(self)
354 }
355 #[doc = "Bit 6 - Advanced Encryption Standard Accelerator access control bit"]
356 #[inline(always)]
357 #[must_use]
358 pub fn crypto0(&mut self) -> CRYPTO0_W<6> {
359 CRYPTO0_W::new(self)
360 }
361 #[doc = "Bit 7 - Capacitive touch sense module access control bit"]
362 #[inline(always)]
363 #[must_use]
364 pub fn csen(&mut self) -> CSEN_W<7> {
365 CSEN_W::new(self)
366 }
367 #[doc = "Bit 8 - Digital to Analog Converter 0 access control bit"]
368 #[inline(always)]
369 #[must_use]
370 pub fn vdac0(&mut self) -> VDAC0_W<8> {
371 VDAC0_W::new(self)
372 }
373 #[doc = "Bit 9 - Peripheral Reflex System access control bit"]
374 #[inline(always)]
375 #[must_use]
376 pub fn prs(&mut self) -> PRS_W<9> {
377 PRS_W::new(self)
378 }
379 #[doc = "Bit 10 - Energy Management Unit access control bit"]
380 #[inline(always)]
381 #[must_use]
382 pub fn emu(&mut self) -> EMU_W<10> {
383 EMU_W::new(self)
384 }
385 #[doc = "Bit 11 - General Purpose CRC access control bit"]
386 #[inline(always)]
387 #[must_use]
388 pub fn gpcrc(&mut self) -> GPCRC_W<11> {
389 GPCRC_W::new(self)
390 }
391 #[doc = "Bit 12 - General purpose Input/Output access control bit"]
392 #[inline(always)]
393 #[must_use]
394 pub fn gpio(&mut self) -> GPIO_W<12> {
395 GPIO_W::new(self)
396 }
397 #[doc = "Bit 13 - I2C 0 access control bit"]
398 #[inline(always)]
399 #[must_use]
400 pub fn i2c0(&mut self) -> I2C0_W<13> {
401 I2C0_W::new(self)
402 }
403 #[doc = "Bit 14 - I2C 1 access control bit"]
404 #[inline(always)]
405 #[must_use]
406 pub fn i2c1(&mut self) -> I2C1_W<14> {
407 I2C1_W::new(self)
408 }
409 #[doc = "Bit 15 - Memory System Controller access control bit"]
410 #[inline(always)]
411 #[must_use]
412 pub fn msc(&mut self) -> MSC_W<15> {
413 MSC_W::new(self)
414 }
415 #[doc = "Bit 17 - Linked Direct Memory Access Controller access control bit"]
416 #[inline(always)]
417 #[must_use]
418 pub fn ldma(&mut self) -> LDMA_W<17> {
419 LDMA_W::new(self)
420 }
421 #[doc = "Bit 18 - Low Energy Sensor Interface access control bit"]
422 #[inline(always)]
423 #[must_use]
424 pub fn lesense(&mut self) -> LESENSE_W<18> {
425 LESENSE_W::new(self)
426 }
427 #[doc = "Bit 19 - Low Energy Timer 0 access control bit"]
428 #[inline(always)]
429 #[must_use]
430 pub fn letimer0(&mut self) -> LETIMER0_W<19> {
431 LETIMER0_W::new(self)
432 }
433 #[doc = "Bit 20 - Low Energy UART 0 access control bit"]
434 #[inline(always)]
435 #[must_use]
436 pub fn leuart0(&mut self) -> LEUART0_W<20> {
437 LEUART0_W::new(self)
438 }
439 #[doc = "Bit 21 - Pulse Counter 0 access control bit"]
440 #[inline(always)]
441 #[must_use]
442 pub fn pcnt0(&mut self) -> PCNT0_W<21> {
443 PCNT0_W::new(self)
444 }
445 #[doc = "Bit 22 - Reset Management Unit access control bit"]
446 #[inline(always)]
447 #[must_use]
448 pub fn rmu(&mut self) -> RMU_W<22> {
449 RMU_W::new(self)
450 }
451 #[doc = "Bit 23 - Real-Time Counter and Calendar access control bit"]
452 #[inline(always)]
453 #[must_use]
454 pub fn rtcc(&mut self) -> RTCC_W<23> {
455 RTCC_W::new(self)
456 }
457 #[doc = "Bit 24 - Security Management Unit access control bit"]
458 #[inline(always)]
459 #[must_use]
460 pub fn smu(&mut self) -> SMU_W<24> {
461 SMU_W::new(self)
462 }
463 #[doc = "Bit 25 - Timer 0 access control bit"]
464 #[inline(always)]
465 #[must_use]
466 pub fn timer0(&mut self) -> TIMER0_W<25> {
467 TIMER0_W::new(self)
468 }
469 #[doc = "Bit 26 - Timer 1 access control bit"]
470 #[inline(always)]
471 #[must_use]
472 pub fn timer1(&mut self) -> TIMER1_W<26> {
473 TIMER1_W::new(self)
474 }
475 #[doc = "Bit 27 - True Random Number Generator 0 access control bit"]
476 #[inline(always)]
477 #[must_use]
478 pub fn trng0(&mut self) -> TRNG0_W<27> {
479 TRNG0_W::new(self)
480 }
481 #[doc = "Bit 28 - Universal Asynchronous Receiver/Transmitter 0 access control bit"]
482 #[inline(always)]
483 #[must_use]
484 pub fn uart0(&mut self) -> UART0_W<28> {
485 UART0_W::new(self)
486 }
487 #[doc = "Bit 29 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
488 #[inline(always)]
489 #[must_use]
490 pub fn usart0(&mut self) -> USART0_W<29> {
491 USART0_W::new(self)
492 }
493 #[doc = "Bit 30 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
494 #[inline(always)]
495 #[must_use]
496 pub fn usart1(&mut self) -> USART1_W<30> {
497 USART1_W::new(self)
498 }
499 #[doc = "Bit 31 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
500 #[inline(always)]
501 #[must_use]
502 pub fn usart2(&mut self) -> USART2_W<31> {
503 USART2_W::new(self)
504 }
505 #[doc = "Writes raw bits to the register."]
506 #[inline(always)]
507 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
508 self.0.bits(bits);
509 self
510 }
511}
512#[doc = "PPU Privilege Access Type Descriptor 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ppupatd0](index.html) module"]
513pub struct PPUPATD0_SPEC;
514impl crate::RegisterSpec for PPUPATD0_SPEC {
515 type Ux = u32;
516}
517#[doc = "`read()` method returns [ppupatd0::R](R) reader structure"]
518impl crate::Readable for PPUPATD0_SPEC {
519 type Reader = R;
520}
521#[doc = "`write(|w| ..)` method takes [ppupatd0::W](W) writer structure"]
522impl crate::Writable for PPUPATD0_SPEC {
523 type Writer = W;
524 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
525 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
526}
527#[doc = "`reset()` method sets PPUPATD0 to value 0"]
528impl crate::Resettable for PPUPATD0_SPEC {
529 const RESET_VALUE: Self::Ux = 0;
530}