efm32tg11b_pac/efm32tg11b120/adc0/
singlectrlx.rs

1#[doc = "Register `SINGLECTRLX` reader"]
2pub struct R(crate::R<SINGLECTRLX_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SINGLECTRLX_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SINGLECTRLX_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SINGLECTRLX_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SINGLECTRLX` writer"]
17pub struct W(crate::W<SINGLECTRLX_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SINGLECTRLX_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SINGLECTRLX_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SINGLECTRLX_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `VREFSEL` reader - Single Channel Reference Selection"]
38pub type VREFSEL_R = crate::FieldReader<u8, VREFSEL_A>;
39#[doc = "Single Channel Reference Selection\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum VREFSEL_A {
43    #[doc = "0: Internal 0.83V Bandgap reference"]
44    VBGR = 0,
45    #[doc = "1: Scaled AVDD: AVDD*(the VREF attenuation factor)"]
46    VDDXWATT = 1,
47    #[doc = "2: Scaled singled ended external Vref: ADCn_EXTP*(the VREF attenuation factor)"]
48    VREFPWATT = 2,
49    #[doc = "3: Raw single ended external Vref: ADCn_EXTP"]
50    VREFP = 3,
51    #[doc = "4: Special mode used to generate ENTROPY."]
52    VENTROPY = 4,
53    #[doc = "5: Scaled differential external Vref from : (ADCn_EXTP-ADCn_EXTN)*(the VREF attenuation factor)"]
54    VREFPNWATT = 5,
55    #[doc = "6: Raw differential external Vref from : (ADCn_EXTP-ADCn_EXTN)"]
56    VREFPN = 6,
57    #[doc = "7: Internal Bandgap reference at low setting 0.78V"]
58    VBGRLOW = 7,
59}
60impl From<VREFSEL_A> for u8 {
61    #[inline(always)]
62    fn from(variant: VREFSEL_A) -> Self {
63        variant as _
64    }
65}
66impl VREFSEL_R {
67    #[doc = "Get enumerated values variant"]
68    #[inline(always)]
69    pub fn variant(&self) -> VREFSEL_A {
70        match self.bits {
71            0 => VREFSEL_A::VBGR,
72            1 => VREFSEL_A::VDDXWATT,
73            2 => VREFSEL_A::VREFPWATT,
74            3 => VREFSEL_A::VREFP,
75            4 => VREFSEL_A::VENTROPY,
76            5 => VREFSEL_A::VREFPNWATT,
77            6 => VREFSEL_A::VREFPN,
78            7 => VREFSEL_A::VBGRLOW,
79            _ => unreachable!(),
80        }
81    }
82    #[doc = "Checks if the value of the field is `VBGR`"]
83    #[inline(always)]
84    pub fn is_vbgr(&self) -> bool {
85        *self == VREFSEL_A::VBGR
86    }
87    #[doc = "Checks if the value of the field is `VDDXWATT`"]
88    #[inline(always)]
89    pub fn is_vddxwatt(&self) -> bool {
90        *self == VREFSEL_A::VDDXWATT
91    }
92    #[doc = "Checks if the value of the field is `VREFPWATT`"]
93    #[inline(always)]
94    pub fn is_vrefpwatt(&self) -> bool {
95        *self == VREFSEL_A::VREFPWATT
96    }
97    #[doc = "Checks if the value of the field is `VREFP`"]
98    #[inline(always)]
99    pub fn is_vrefp(&self) -> bool {
100        *self == VREFSEL_A::VREFP
101    }
102    #[doc = "Checks if the value of the field is `VENTROPY`"]
103    #[inline(always)]
104    pub fn is_ventropy(&self) -> bool {
105        *self == VREFSEL_A::VENTROPY
106    }
107    #[doc = "Checks if the value of the field is `VREFPNWATT`"]
108    #[inline(always)]
109    pub fn is_vrefpnwatt(&self) -> bool {
110        *self == VREFSEL_A::VREFPNWATT
111    }
112    #[doc = "Checks if the value of the field is `VREFPN`"]
113    #[inline(always)]
114    pub fn is_vrefpn(&self) -> bool {
115        *self == VREFSEL_A::VREFPN
116    }
117    #[doc = "Checks if the value of the field is `VBGRLOW`"]
118    #[inline(always)]
119    pub fn is_vbgrlow(&self) -> bool {
120        *self == VREFSEL_A::VBGRLOW
121    }
122}
123#[doc = "Field `VREFSEL` writer - Single Channel Reference Selection"]
124pub type VREFSEL_W<'a, const O: u8> =
125    crate::FieldWriterSafe<'a, u32, SINGLECTRLX_SPEC, u8, VREFSEL_A, 3, O>;
126impl<'a, const O: u8> VREFSEL_W<'a, O> {
127    #[doc = "Internal 0.83V Bandgap reference"]
128    #[inline(always)]
129    pub fn vbgr(self) -> &'a mut W {
130        self.variant(VREFSEL_A::VBGR)
131    }
132    #[doc = "Scaled AVDD: AVDD*(the VREF attenuation factor)"]
133    #[inline(always)]
134    pub fn vddxwatt(self) -> &'a mut W {
135        self.variant(VREFSEL_A::VDDXWATT)
136    }
137    #[doc = "Scaled singled ended external Vref: ADCn_EXTP*(the VREF attenuation factor)"]
138    #[inline(always)]
139    pub fn vrefpwatt(self) -> &'a mut W {
140        self.variant(VREFSEL_A::VREFPWATT)
141    }
142    #[doc = "Raw single ended external Vref: ADCn_EXTP"]
143    #[inline(always)]
144    pub fn vrefp(self) -> &'a mut W {
145        self.variant(VREFSEL_A::VREFP)
146    }
147    #[doc = "Special mode used to generate ENTROPY."]
148    #[inline(always)]
149    pub fn ventropy(self) -> &'a mut W {
150        self.variant(VREFSEL_A::VENTROPY)
151    }
152    #[doc = "Scaled differential external Vref from : (ADCn_EXTP-ADCn_EXTN)*(the VREF attenuation factor)"]
153    #[inline(always)]
154    pub fn vrefpnwatt(self) -> &'a mut W {
155        self.variant(VREFSEL_A::VREFPNWATT)
156    }
157    #[doc = "Raw differential external Vref from : (ADCn_EXTP-ADCn_EXTN)"]
158    #[inline(always)]
159    pub fn vrefpn(self) -> &'a mut W {
160        self.variant(VREFSEL_A::VREFPN)
161    }
162    #[doc = "Internal Bandgap reference at low setting 0.78V"]
163    #[inline(always)]
164    pub fn vbgrlow(self) -> &'a mut W {
165        self.variant(VREFSEL_A::VBGRLOW)
166    }
167}
168#[doc = "Field `VREFATTFIX` reader - Enable Fixed Scaling on VREF"]
169pub type VREFATTFIX_R = crate::BitReader<bool>;
170#[doc = "Field `VREFATTFIX` writer - Enable Fixed Scaling on VREF"]
171pub type VREFATTFIX_W<'a, const O: u8> = crate::BitWriter<'a, u32, SINGLECTRLX_SPEC, bool, O>;
172#[doc = "Field `VREFATT` reader - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
173pub type VREFATT_R = crate::FieldReader<u8, u8>;
174#[doc = "Field `VREFATT` writer - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
175pub type VREFATT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SINGLECTRLX_SPEC, u8, u8, 4, O>;
176#[doc = "Field `VINATT` reader - Code for VIN Attenuation Factor"]
177pub type VINATT_R = crate::FieldReader<u8, u8>;
178#[doc = "Field `VINATT` writer - Code for VIN Attenuation Factor"]
179pub type VINATT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SINGLECTRLX_SPEC, u8, u8, 4, O>;
180#[doc = "Field `DVL` reader - Single Channel DV Level Select"]
181pub type DVL_R = crate::FieldReader<u8, u8>;
182#[doc = "Field `DVL` writer - Single Channel DV Level Select"]
183pub type DVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SINGLECTRLX_SPEC, u8, u8, 2, O>;
184#[doc = "Field `FIFOOFACT` reader - Single Channel FIFO Overflow Action"]
185pub type FIFOOFACT_R = crate::BitReader<bool>;
186#[doc = "Field `FIFOOFACT` writer - Single Channel FIFO Overflow Action"]
187pub type FIFOOFACT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SINGLECTRLX_SPEC, bool, O>;
188#[doc = "Field `PRSMODE` reader - Single Channel PRS Trigger Mode"]
189pub type PRSMODE_R = crate::BitReader<bool>;
190#[doc = "Field `PRSMODE` writer - Single Channel PRS Trigger Mode"]
191pub type PRSMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SINGLECTRLX_SPEC, bool, O>;
192#[doc = "Field `PRSSEL` reader - Single Channel PRS Trigger Select"]
193pub type PRSSEL_R = crate::FieldReader<u8, PRSSEL_A>;
194#[doc = "Single Channel PRS Trigger Select\n\nValue on reset: 0"]
195#[derive(Clone, Copy, Debug, PartialEq, Eq)]
196#[repr(u8)]
197pub enum PRSSEL_A {
198    #[doc = "0: PRS ch 0 triggers single channel"]
199    PRSCH0 = 0,
200    #[doc = "1: PRS ch 1 triggers single channel"]
201    PRSCH1 = 1,
202    #[doc = "2: PRS ch 2 triggers single channel"]
203    PRSCH2 = 2,
204    #[doc = "3: PRS ch 3 triggers single channel"]
205    PRSCH3 = 3,
206    #[doc = "4: PRS ch 4 triggers single channel"]
207    PRSCH4 = 4,
208    #[doc = "5: PRS ch 5 triggers single channel"]
209    PRSCH5 = 5,
210    #[doc = "6: PRS ch 6 triggers single channel"]
211    PRSCH6 = 6,
212    #[doc = "7: PRS ch 7 triggers single channel"]
213    PRSCH7 = 7,
214}
215impl From<PRSSEL_A> for u8 {
216    #[inline(always)]
217    fn from(variant: PRSSEL_A) -> Self {
218        variant as _
219    }
220}
221impl PRSSEL_R {
222    #[doc = "Get enumerated values variant"]
223    #[inline(always)]
224    pub fn variant(&self) -> PRSSEL_A {
225        match self.bits {
226            0 => PRSSEL_A::PRSCH0,
227            1 => PRSSEL_A::PRSCH1,
228            2 => PRSSEL_A::PRSCH2,
229            3 => PRSSEL_A::PRSCH3,
230            4 => PRSSEL_A::PRSCH4,
231            5 => PRSSEL_A::PRSCH5,
232            6 => PRSSEL_A::PRSCH6,
233            7 => PRSSEL_A::PRSCH7,
234            _ => unreachable!(),
235        }
236    }
237    #[doc = "Checks if the value of the field is `PRSCH0`"]
238    #[inline(always)]
239    pub fn is_prsch0(&self) -> bool {
240        *self == PRSSEL_A::PRSCH0
241    }
242    #[doc = "Checks if the value of the field is `PRSCH1`"]
243    #[inline(always)]
244    pub fn is_prsch1(&self) -> bool {
245        *self == PRSSEL_A::PRSCH1
246    }
247    #[doc = "Checks if the value of the field is `PRSCH2`"]
248    #[inline(always)]
249    pub fn is_prsch2(&self) -> bool {
250        *self == PRSSEL_A::PRSCH2
251    }
252    #[doc = "Checks if the value of the field is `PRSCH3`"]
253    #[inline(always)]
254    pub fn is_prsch3(&self) -> bool {
255        *self == PRSSEL_A::PRSCH3
256    }
257    #[doc = "Checks if the value of the field is `PRSCH4`"]
258    #[inline(always)]
259    pub fn is_prsch4(&self) -> bool {
260        *self == PRSSEL_A::PRSCH4
261    }
262    #[doc = "Checks if the value of the field is `PRSCH5`"]
263    #[inline(always)]
264    pub fn is_prsch5(&self) -> bool {
265        *self == PRSSEL_A::PRSCH5
266    }
267    #[doc = "Checks if the value of the field is `PRSCH6`"]
268    #[inline(always)]
269    pub fn is_prsch6(&self) -> bool {
270        *self == PRSSEL_A::PRSCH6
271    }
272    #[doc = "Checks if the value of the field is `PRSCH7`"]
273    #[inline(always)]
274    pub fn is_prsch7(&self) -> bool {
275        *self == PRSSEL_A::PRSCH7
276    }
277}
278#[doc = "Field `PRSSEL` writer - Single Channel PRS Trigger Select"]
279pub type PRSSEL_W<'a, const O: u8> =
280    crate::FieldWriterSafe<'a, u32, SINGLECTRLX_SPEC, u8, PRSSEL_A, 3, O>;
281impl<'a, const O: u8> PRSSEL_W<'a, O> {
282    #[doc = "PRS ch 0 triggers single channel"]
283    #[inline(always)]
284    pub fn prsch0(self) -> &'a mut W {
285        self.variant(PRSSEL_A::PRSCH0)
286    }
287    #[doc = "PRS ch 1 triggers single channel"]
288    #[inline(always)]
289    pub fn prsch1(self) -> &'a mut W {
290        self.variant(PRSSEL_A::PRSCH1)
291    }
292    #[doc = "PRS ch 2 triggers single channel"]
293    #[inline(always)]
294    pub fn prsch2(self) -> &'a mut W {
295        self.variant(PRSSEL_A::PRSCH2)
296    }
297    #[doc = "PRS ch 3 triggers single channel"]
298    #[inline(always)]
299    pub fn prsch3(self) -> &'a mut W {
300        self.variant(PRSSEL_A::PRSCH3)
301    }
302    #[doc = "PRS ch 4 triggers single channel"]
303    #[inline(always)]
304    pub fn prsch4(self) -> &'a mut W {
305        self.variant(PRSSEL_A::PRSCH4)
306    }
307    #[doc = "PRS ch 5 triggers single channel"]
308    #[inline(always)]
309    pub fn prsch5(self) -> &'a mut W {
310        self.variant(PRSSEL_A::PRSCH5)
311    }
312    #[doc = "PRS ch 6 triggers single channel"]
313    #[inline(always)]
314    pub fn prsch6(self) -> &'a mut W {
315        self.variant(PRSSEL_A::PRSCH6)
316    }
317    #[doc = "PRS ch 7 triggers single channel"]
318    #[inline(always)]
319    pub fn prsch7(self) -> &'a mut W {
320        self.variant(PRSSEL_A::PRSCH7)
321    }
322}
323#[doc = "Field `CONVSTARTDELAY` reader - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set"]
324pub type CONVSTARTDELAY_R = crate::FieldReader<u8, u8>;
325#[doc = "Field `CONVSTARTDELAY` writer - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set"]
326pub type CONVSTARTDELAY_W<'a, const O: u8> =
327    crate::FieldWriter<'a, u32, SINGLECTRLX_SPEC, u8, u8, 5, O>;
328#[doc = "Field `CONVSTARTDELAYEN` reader - Enable Delaying Next Conversion Start"]
329pub type CONVSTARTDELAYEN_R = crate::BitReader<bool>;
330#[doc = "Field `CONVSTARTDELAYEN` writer - Enable Delaying Next Conversion Start"]
331pub type CONVSTARTDELAYEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SINGLECTRLX_SPEC, bool, O>;
332#[doc = "Field `REPDELAY` reader - REPDELAY Select for SINGLE REP Mode"]
333pub type REPDELAY_R = crate::FieldReader<u8, REPDELAY_A>;
334#[doc = "REPDELAY Select for SINGLE REP Mode\n\nValue on reset: 0"]
335#[derive(Clone, Copy, Debug, PartialEq, Eq)]
336#[repr(u8)]
337pub enum REPDELAY_A {
338    #[doc = "0: No delay"]
339    NODELAY = 0,
340    #[doc = "1: 4 conversion clock cycles"]
341    _4CYCLES = 1,
342    #[doc = "2: 8 conversion clock cycles"]
343    _8CYCLES = 2,
344    #[doc = "3: 16 conversion clock cycles"]
345    _16CYCLES = 3,
346    #[doc = "4: 32 conversion clock cycles"]
347    _32CYCLES = 4,
348    #[doc = "5: 64 conversion clock cycles"]
349    _64CYCLES = 5,
350    #[doc = "6: 128 conversion clock cycles"]
351    _128CYCLES = 6,
352    #[doc = "7: 256 conversion clock cycles"]
353    _256CYCLES = 7,
354}
355impl From<REPDELAY_A> for u8 {
356    #[inline(always)]
357    fn from(variant: REPDELAY_A) -> Self {
358        variant as _
359    }
360}
361impl REPDELAY_R {
362    #[doc = "Get enumerated values variant"]
363    #[inline(always)]
364    pub fn variant(&self) -> REPDELAY_A {
365        match self.bits {
366            0 => REPDELAY_A::NODELAY,
367            1 => REPDELAY_A::_4CYCLES,
368            2 => REPDELAY_A::_8CYCLES,
369            3 => REPDELAY_A::_16CYCLES,
370            4 => REPDELAY_A::_32CYCLES,
371            5 => REPDELAY_A::_64CYCLES,
372            6 => REPDELAY_A::_128CYCLES,
373            7 => REPDELAY_A::_256CYCLES,
374            _ => unreachable!(),
375        }
376    }
377    #[doc = "Checks if the value of the field is `NODELAY`"]
378    #[inline(always)]
379    pub fn is_nodelay(&self) -> bool {
380        *self == REPDELAY_A::NODELAY
381    }
382    #[doc = "Checks if the value of the field is `_4CYCLES`"]
383    #[inline(always)]
384    pub fn is_4cycles(&self) -> bool {
385        *self == REPDELAY_A::_4CYCLES
386    }
387    #[doc = "Checks if the value of the field is `_8CYCLES`"]
388    #[inline(always)]
389    pub fn is_8cycles(&self) -> bool {
390        *self == REPDELAY_A::_8CYCLES
391    }
392    #[doc = "Checks if the value of the field is `_16CYCLES`"]
393    #[inline(always)]
394    pub fn is_16cycles(&self) -> bool {
395        *self == REPDELAY_A::_16CYCLES
396    }
397    #[doc = "Checks if the value of the field is `_32CYCLES`"]
398    #[inline(always)]
399    pub fn is_32cycles(&self) -> bool {
400        *self == REPDELAY_A::_32CYCLES
401    }
402    #[doc = "Checks if the value of the field is `_64CYCLES`"]
403    #[inline(always)]
404    pub fn is_64cycles(&self) -> bool {
405        *self == REPDELAY_A::_64CYCLES
406    }
407    #[doc = "Checks if the value of the field is `_128CYCLES`"]
408    #[inline(always)]
409    pub fn is_128cycles(&self) -> bool {
410        *self == REPDELAY_A::_128CYCLES
411    }
412    #[doc = "Checks if the value of the field is `_256CYCLES`"]
413    #[inline(always)]
414    pub fn is_256cycles(&self) -> bool {
415        *self == REPDELAY_A::_256CYCLES
416    }
417}
418#[doc = "Field `REPDELAY` writer - REPDELAY Select for SINGLE REP Mode"]
419pub type REPDELAY_W<'a, const O: u8> =
420    crate::FieldWriterSafe<'a, u32, SINGLECTRLX_SPEC, u8, REPDELAY_A, 3, O>;
421impl<'a, const O: u8> REPDELAY_W<'a, O> {
422    #[doc = "No delay"]
423    #[inline(always)]
424    pub fn nodelay(self) -> &'a mut W {
425        self.variant(REPDELAY_A::NODELAY)
426    }
427    #[doc = "4 conversion clock cycles"]
428    #[inline(always)]
429    pub fn _4cycles(self) -> &'a mut W {
430        self.variant(REPDELAY_A::_4CYCLES)
431    }
432    #[doc = "8 conversion clock cycles"]
433    #[inline(always)]
434    pub fn _8cycles(self) -> &'a mut W {
435        self.variant(REPDELAY_A::_8CYCLES)
436    }
437    #[doc = "16 conversion clock cycles"]
438    #[inline(always)]
439    pub fn _16cycles(self) -> &'a mut W {
440        self.variant(REPDELAY_A::_16CYCLES)
441    }
442    #[doc = "32 conversion clock cycles"]
443    #[inline(always)]
444    pub fn _32cycles(self) -> &'a mut W {
445        self.variant(REPDELAY_A::_32CYCLES)
446    }
447    #[doc = "64 conversion clock cycles"]
448    #[inline(always)]
449    pub fn _64cycles(self) -> &'a mut W {
450        self.variant(REPDELAY_A::_64CYCLES)
451    }
452    #[doc = "128 conversion clock cycles"]
453    #[inline(always)]
454    pub fn _128cycles(self) -> &'a mut W {
455        self.variant(REPDELAY_A::_128CYCLES)
456    }
457    #[doc = "256 conversion clock cycles"]
458    #[inline(always)]
459    pub fn _256cycles(self) -> &'a mut W {
460        self.variant(REPDELAY_A::_256CYCLES)
461    }
462}
463impl R {
464    #[doc = "Bits 0:2 - Single Channel Reference Selection"]
465    #[inline(always)]
466    pub fn vrefsel(&self) -> VREFSEL_R {
467        VREFSEL_R::new((self.bits & 7) as u8)
468    }
469    #[doc = "Bit 3 - Enable Fixed Scaling on VREF"]
470    #[inline(always)]
471    pub fn vrefattfix(&self) -> VREFATTFIX_R {
472        VREFATTFIX_R::new(((self.bits >> 3) & 1) != 0)
473    }
474    #[doc = "Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
475    #[inline(always)]
476    pub fn vrefatt(&self) -> VREFATT_R {
477        VREFATT_R::new(((self.bits >> 4) & 0x0f) as u8)
478    }
479    #[doc = "Bits 8:11 - Code for VIN Attenuation Factor"]
480    #[inline(always)]
481    pub fn vinatt(&self) -> VINATT_R {
482        VINATT_R::new(((self.bits >> 8) & 0x0f) as u8)
483    }
484    #[doc = "Bits 12:13 - Single Channel DV Level Select"]
485    #[inline(always)]
486    pub fn dvl(&self) -> DVL_R {
487        DVL_R::new(((self.bits >> 12) & 3) as u8)
488    }
489    #[doc = "Bit 14 - Single Channel FIFO Overflow Action"]
490    #[inline(always)]
491    pub fn fifoofact(&self) -> FIFOOFACT_R {
492        FIFOOFACT_R::new(((self.bits >> 14) & 1) != 0)
493    }
494    #[doc = "Bit 16 - Single Channel PRS Trigger Mode"]
495    #[inline(always)]
496    pub fn prsmode(&self) -> PRSMODE_R {
497        PRSMODE_R::new(((self.bits >> 16) & 1) != 0)
498    }
499    #[doc = "Bits 17:19 - Single Channel PRS Trigger Select"]
500    #[inline(always)]
501    pub fn prssel(&self) -> PRSSEL_R {
502        PRSSEL_R::new(((self.bits >> 17) & 7) as u8)
503    }
504    #[doc = "Bits 22:26 - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set"]
505    #[inline(always)]
506    pub fn convstartdelay(&self) -> CONVSTARTDELAY_R {
507        CONVSTARTDELAY_R::new(((self.bits >> 22) & 0x1f) as u8)
508    }
509    #[doc = "Bit 27 - Enable Delaying Next Conversion Start"]
510    #[inline(always)]
511    pub fn convstartdelayen(&self) -> CONVSTARTDELAYEN_R {
512        CONVSTARTDELAYEN_R::new(((self.bits >> 27) & 1) != 0)
513    }
514    #[doc = "Bits 29:31 - REPDELAY Select for SINGLE REP Mode"]
515    #[inline(always)]
516    pub fn repdelay(&self) -> REPDELAY_R {
517        REPDELAY_R::new(((self.bits >> 29) & 7) as u8)
518    }
519}
520impl W {
521    #[doc = "Bits 0:2 - Single Channel Reference Selection"]
522    #[inline(always)]
523    #[must_use]
524    pub fn vrefsel(&mut self) -> VREFSEL_W<0> {
525        VREFSEL_W::new(self)
526    }
527    #[doc = "Bit 3 - Enable Fixed Scaling on VREF"]
528    #[inline(always)]
529    #[must_use]
530    pub fn vrefattfix(&mut self) -> VREFATTFIX_W<3> {
531        VREFATTFIX_W::new(self)
532    }
533    #[doc = "Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
534    #[inline(always)]
535    #[must_use]
536    pub fn vrefatt(&mut self) -> VREFATT_W<4> {
537        VREFATT_W::new(self)
538    }
539    #[doc = "Bits 8:11 - Code for VIN Attenuation Factor"]
540    #[inline(always)]
541    #[must_use]
542    pub fn vinatt(&mut self) -> VINATT_W<8> {
543        VINATT_W::new(self)
544    }
545    #[doc = "Bits 12:13 - Single Channel DV Level Select"]
546    #[inline(always)]
547    #[must_use]
548    pub fn dvl(&mut self) -> DVL_W<12> {
549        DVL_W::new(self)
550    }
551    #[doc = "Bit 14 - Single Channel FIFO Overflow Action"]
552    #[inline(always)]
553    #[must_use]
554    pub fn fifoofact(&mut self) -> FIFOOFACT_W<14> {
555        FIFOOFACT_W::new(self)
556    }
557    #[doc = "Bit 16 - Single Channel PRS Trigger Mode"]
558    #[inline(always)]
559    #[must_use]
560    pub fn prsmode(&mut self) -> PRSMODE_W<16> {
561        PRSMODE_W::new(self)
562    }
563    #[doc = "Bits 17:19 - Single Channel PRS Trigger Select"]
564    #[inline(always)]
565    #[must_use]
566    pub fn prssel(&mut self) -> PRSSEL_W<17> {
567        PRSSEL_W::new(self)
568    }
569    #[doc = "Bits 22:26 - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set"]
570    #[inline(always)]
571    #[must_use]
572    pub fn convstartdelay(&mut self) -> CONVSTARTDELAY_W<22> {
573        CONVSTARTDELAY_W::new(self)
574    }
575    #[doc = "Bit 27 - Enable Delaying Next Conversion Start"]
576    #[inline(always)]
577    #[must_use]
578    pub fn convstartdelayen(&mut self) -> CONVSTARTDELAYEN_W<27> {
579        CONVSTARTDELAYEN_W::new(self)
580    }
581    #[doc = "Bits 29:31 - REPDELAY Select for SINGLE REP Mode"]
582    #[inline(always)]
583    #[must_use]
584    pub fn repdelay(&mut self) -> REPDELAY_W<29> {
585        REPDELAY_W::new(self)
586    }
587    #[doc = "Writes raw bits to the register."]
588    #[inline(always)]
589    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
590        self.0.bits(bits);
591        self
592    }
593}
594#[doc = "Single Channel Control Register Continued\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [singlectrlx](index.html) module"]
595pub struct SINGLECTRLX_SPEC;
596impl crate::RegisterSpec for SINGLECTRLX_SPEC {
597    type Ux = u32;
598}
599#[doc = "`read()` method returns [singlectrlx::R](R) reader structure"]
600impl crate::Readable for SINGLECTRLX_SPEC {
601    type Reader = R;
602}
603#[doc = "`write(|w| ..)` method takes [singlectrlx::W](W) writer structure"]
604impl crate::Writable for SINGLECTRLX_SPEC {
605    type Writer = W;
606    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
607    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
608}
609#[doc = "`reset()` method sets SINGLECTRLX to value 0"]
610impl crate::Resettable for SINGLECTRLX_SPEC {
611    const RESET_VALUE: Self::Ux = 0;
612}
efm32tg11b_pac/efm32tg11b120/adc0/singlectrlx.rs

efm32tg11b_pac/efm32tg11b120/adc0/
singlectrlx.rs
