efm32tg108_pac/dma/
ch5_ctrl.rs

1#[doc = "Register `CH5_CTRL` reader"]
2pub struct R(crate::R<CH5_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH5_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH5_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH5_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH5_CTRL` writer"]
17pub struct W(crate::W<CH5_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH5_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH5_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH5_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH5_CTRL_SPEC, u8, u8, 4, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "13: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
48    USART1 = 13,
49    #[doc = "16: Low Energy UART 0"]
50    LEUART0 = 16,
51    #[doc = "20: I2C 0"]
52    I2C0 = 20,
53    #[doc = "24: Timer 0"]
54    TIMER0 = 24,
55    #[doc = "25: Timer 1"]
56    TIMER1 = 25,
57    #[doc = "48: `110000`"]
58    MSC = 48,
59    #[doc = "50: Low Energy Sensor Interface"]
60    LESENSE = 50,
61}
62impl From<SOURCESEL_A> for u8 {
63    #[inline(always)]
64    fn from(variant: SOURCESEL_A) -> Self {
65        variant as _
66    }
67}
68#[doc = "Field `SOURCESEL` reader - Source Select"]
69pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
70impl SOURCESEL_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> Option<SOURCESEL_A> {
74        match self.bits {
75            0 => Some(SOURCESEL_A::NONE),
76            13 => Some(SOURCESEL_A::USART1),
77            16 => Some(SOURCESEL_A::LEUART0),
78            20 => Some(SOURCESEL_A::I2C0),
79            24 => Some(SOURCESEL_A::TIMER0),
80            25 => Some(SOURCESEL_A::TIMER1),
81            48 => Some(SOURCESEL_A::MSC),
82            50 => Some(SOURCESEL_A::LESENSE),
83            _ => None,
84        }
85    }
86    #[doc = "Checks if the value of the field is `NONE`"]
87    #[inline(always)]
88    pub fn is_none(&self) -> bool {
89        *self == SOURCESEL_A::NONE
90    }
91    #[doc = "Checks if the value of the field is `USART1`"]
92    #[inline(always)]
93    pub fn is_usart1(&self) -> bool {
94        *self == SOURCESEL_A::USART1
95    }
96    #[doc = "Checks if the value of the field is `LEUART0`"]
97    #[inline(always)]
98    pub fn is_leuart0(&self) -> bool {
99        *self == SOURCESEL_A::LEUART0
100    }
101    #[doc = "Checks if the value of the field is `I2C0`"]
102    #[inline(always)]
103    pub fn is_i2c0(&self) -> bool {
104        *self == SOURCESEL_A::I2C0
105    }
106    #[doc = "Checks if the value of the field is `TIMER0`"]
107    #[inline(always)]
108    pub fn is_timer0(&self) -> bool {
109        *self == SOURCESEL_A::TIMER0
110    }
111    #[doc = "Checks if the value of the field is `TIMER1`"]
112    #[inline(always)]
113    pub fn is_timer1(&self) -> bool {
114        *self == SOURCESEL_A::TIMER1
115    }
116    #[doc = "Checks if the value of the field is `MSC`"]
117    #[inline(always)]
118    pub fn is_msc(&self) -> bool {
119        *self == SOURCESEL_A::MSC
120    }
121    #[doc = "Checks if the value of the field is `LESENSE`"]
122    #[inline(always)]
123    pub fn is_lesense(&self) -> bool {
124        *self == SOURCESEL_A::LESENSE
125    }
126}
127#[doc = "Field `SOURCESEL` writer - Source Select"]
128pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH5_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
129impl<'a> SOURCESEL_W<'a> {
130    #[doc = "No source selected"]
131    #[inline(always)]
132    pub fn none(self) -> &'a mut W {
133        self.variant(SOURCESEL_A::NONE)
134    }
135    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
136    #[inline(always)]
137    pub fn usart1(self) -> &'a mut W {
138        self.variant(SOURCESEL_A::USART1)
139    }
140    #[doc = "Low Energy UART 0"]
141    #[inline(always)]
142    pub fn leuart0(self) -> &'a mut W {
143        self.variant(SOURCESEL_A::LEUART0)
144    }
145    #[doc = "I2C 0"]
146    #[inline(always)]
147    pub fn i2c0(self) -> &'a mut W {
148        self.variant(SOURCESEL_A::I2C0)
149    }
150    #[doc = "Timer 0"]
151    #[inline(always)]
152    pub fn timer0(self) -> &'a mut W {
153        self.variant(SOURCESEL_A::TIMER0)
154    }
155    #[doc = "Timer 1"]
156    #[inline(always)]
157    pub fn timer1(self) -> &'a mut W {
158        self.variant(SOURCESEL_A::TIMER1)
159    }
160    #[doc = "`110000`"]
161    #[inline(always)]
162    pub fn msc(self) -> &'a mut W {
163        self.variant(SOURCESEL_A::MSC)
164    }
165    #[doc = "Low Energy Sensor Interface"]
166    #[inline(always)]
167    pub fn lesense(self) -> &'a mut W {
168        self.variant(SOURCESEL_A::LESENSE)
169    }
170}
171impl R {
172    #[doc = "Bits 0:3 - Signal Select"]
173    #[inline(always)]
174    pub fn sigsel(&self) -> SIGSEL_R {
175        SIGSEL_R::new((self.bits & 0x0f) as u8)
176    }
177    #[doc = "Bits 16:21 - Source Select"]
178    #[inline(always)]
179    pub fn sourcesel(&self) -> SOURCESEL_R {
180        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
181    }
182}
183impl W {
184    #[doc = "Bits 0:3 - Signal Select"]
185    #[inline(always)]
186    pub fn sigsel(&mut self) -> SIGSEL_W {
187        SIGSEL_W::new(self)
188    }
189    #[doc = "Bits 16:21 - Source Select"]
190    #[inline(always)]
191    pub fn sourcesel(&mut self) -> SOURCESEL_W {
192        SOURCESEL_W::new(self)
193    }
194    #[doc = "Writes raw bits to the register."]
195    #[inline(always)]
196    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
197        self.0.bits(bits);
198        self
199    }
200}
201#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch5_ctrl](index.html) module"]
202pub struct CH5_CTRL_SPEC;
203impl crate::RegisterSpec for CH5_CTRL_SPEC {
204    type Ux = u32;
205}
206#[doc = "`read()` method returns [ch5_ctrl::R](R) reader structure"]
207impl crate::Readable for CH5_CTRL_SPEC {
208    type Reader = R;
209}
210#[doc = "`write(|w| ..)` method takes [ch5_ctrl::W](W) writer structure"]
211impl crate::Writable for CH5_CTRL_SPEC {
212    type Writer = W;
213}
214#[doc = "`reset()` method sets CH5_CTRL to value 0"]
215impl crate::Resettable for CH5_CTRL_SPEC {
216    #[inline(always)]
217    fn reset_value() -> Self::Ux {
218        0
219    }
220}
efm32tg108_pac/dma/ch5_ctrl.rs

efm32tg108_pac/dma/
ch5_ctrl.rs
