efm32tg108_pac/cmu/
hfperclken0.rs

1#[doc = "Register `HFPERCLKEN0` reader"]
2pub struct R(crate::R<HFPERCLKEN0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HFPERCLKEN0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HFPERCLKEN0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HFPERCLKEN0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HFPERCLKEN0` writer"]
17pub struct W(crate::W<HFPERCLKEN0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HFPERCLKEN0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HFPERCLKEN0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HFPERCLKEN0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ACMP0` reader - Analog Comparator 0 Clock Enable"]
38pub type ACMP0_R = crate::BitReader<bool>;
39#[doc = "Field `ACMP0` writer - Analog Comparator 0 Clock Enable"]
40pub type ACMP0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 0>;
41#[doc = "Field `ACMP1` reader - Analog Comparator 1 Clock Enable"]
42pub type ACMP1_R = crate::BitReader<bool>;
43#[doc = "Field `ACMP1` writer - Analog Comparator 1 Clock Enable"]
44pub type ACMP1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 1>;
45#[doc = "Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
46pub type USART1_R = crate::BitReader<bool>;
47#[doc = "Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
48pub type USART1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 3>;
49#[doc = "Field `TIMER0` reader - Timer 0 Clock Enable"]
50pub type TIMER0_R = crate::BitReader<bool>;
51#[doc = "Field `TIMER0` writer - Timer 0 Clock Enable"]
52pub type TIMER0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 4>;
53#[doc = "Field `TIMER1` reader - Timer 1 Clock Enable"]
54pub type TIMER1_R = crate::BitReader<bool>;
55#[doc = "Field `TIMER1` writer - Timer 1 Clock Enable"]
56pub type TIMER1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 5>;
57#[doc = "Field `GPIO` reader - General purpose Input/Output Clock Enable"]
58pub type GPIO_R = crate::BitReader<bool>;
59#[doc = "Field `GPIO` writer - General purpose Input/Output Clock Enable"]
60pub type GPIO_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 6>;
61#[doc = "Field `VCMP` reader - Voltage Comparator Clock Enable"]
62pub type VCMP_R = crate::BitReader<bool>;
63#[doc = "Field `VCMP` writer - Voltage Comparator Clock Enable"]
64pub type VCMP_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 7>;
65#[doc = "Field `PRS` reader - Peripheral Reflex System Clock Enable"]
66pub type PRS_R = crate::BitReader<bool>;
67#[doc = "Field `PRS` writer - Peripheral Reflex System Clock Enable"]
68pub type PRS_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 8>;
69#[doc = "Field `I2C0` reader - I2C 0 Clock Enable"]
70pub type I2C0_R = crate::BitReader<bool>;
71#[doc = "Field `I2C0` writer - I2C 0 Clock Enable"]
72pub type I2C0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 11>;
73impl R {
74    #[doc = "Bit 0 - Analog Comparator 0 Clock Enable"]
75    #[inline(always)]
76    pub fn acmp0(&self) -> ACMP0_R {
77        ACMP0_R::new((self.bits & 1) != 0)
78    }
79    #[doc = "Bit 1 - Analog Comparator 1 Clock Enable"]
80    #[inline(always)]
81    pub fn acmp1(&self) -> ACMP1_R {
82        ACMP1_R::new(((self.bits >> 1) & 1) != 0)
83    }
84    #[doc = "Bit 3 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
85    #[inline(always)]
86    pub fn usart1(&self) -> USART1_R {
87        USART1_R::new(((self.bits >> 3) & 1) != 0)
88    }
89    #[doc = "Bit 4 - Timer 0 Clock Enable"]
90    #[inline(always)]
91    pub fn timer0(&self) -> TIMER0_R {
92        TIMER0_R::new(((self.bits >> 4) & 1) != 0)
93    }
94    #[doc = "Bit 5 - Timer 1 Clock Enable"]
95    #[inline(always)]
96    pub fn timer1(&self) -> TIMER1_R {
97        TIMER1_R::new(((self.bits >> 5) & 1) != 0)
98    }
99    #[doc = "Bit 6 - General purpose Input/Output Clock Enable"]
100    #[inline(always)]
101    pub fn gpio(&self) -> GPIO_R {
102        GPIO_R::new(((self.bits >> 6) & 1) != 0)
103    }
104    #[doc = "Bit 7 - Voltage Comparator Clock Enable"]
105    #[inline(always)]
106    pub fn vcmp(&self) -> VCMP_R {
107        VCMP_R::new(((self.bits >> 7) & 1) != 0)
108    }
109    #[doc = "Bit 8 - Peripheral Reflex System Clock Enable"]
110    #[inline(always)]
111    pub fn prs(&self) -> PRS_R {
112        PRS_R::new(((self.bits >> 8) & 1) != 0)
113    }
114    #[doc = "Bit 11 - I2C 0 Clock Enable"]
115    #[inline(always)]
116    pub fn i2c0(&self) -> I2C0_R {
117        I2C0_R::new(((self.bits >> 11) & 1) != 0)
118    }
119}
120impl W {
121    #[doc = "Bit 0 - Analog Comparator 0 Clock Enable"]
122    #[inline(always)]
123    pub fn acmp0(&mut self) -> ACMP0_W {
124        ACMP0_W::new(self)
125    }
126    #[doc = "Bit 1 - Analog Comparator 1 Clock Enable"]
127    #[inline(always)]
128    pub fn acmp1(&mut self) -> ACMP1_W {
129        ACMP1_W::new(self)
130    }
131    #[doc = "Bit 3 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
132    #[inline(always)]
133    pub fn usart1(&mut self) -> USART1_W {
134        USART1_W::new(self)
135    }
136    #[doc = "Bit 4 - Timer 0 Clock Enable"]
137    #[inline(always)]
138    pub fn timer0(&mut self) -> TIMER0_W {
139        TIMER0_W::new(self)
140    }
141    #[doc = "Bit 5 - Timer 1 Clock Enable"]
142    #[inline(always)]
143    pub fn timer1(&mut self) -> TIMER1_W {
144        TIMER1_W::new(self)
145    }
146    #[doc = "Bit 6 - General purpose Input/Output Clock Enable"]
147    #[inline(always)]
148    pub fn gpio(&mut self) -> GPIO_W {
149        GPIO_W::new(self)
150    }
151    #[doc = "Bit 7 - Voltage Comparator Clock Enable"]
152    #[inline(always)]
153    pub fn vcmp(&mut self) -> VCMP_W {
154        VCMP_W::new(self)
155    }
156    #[doc = "Bit 8 - Peripheral Reflex System Clock Enable"]
157    #[inline(always)]
158    pub fn prs(&mut self) -> PRS_W {
159        PRS_W::new(self)
160    }
161    #[doc = "Bit 11 - I2C 0 Clock Enable"]
162    #[inline(always)]
163    pub fn i2c0(&mut self) -> I2C0_W {
164        I2C0_W::new(self)
165    }
166    #[doc = "Writes raw bits to the register."]
167    #[inline(always)]
168    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
169        self.0.bits(bits);
170        self
171    }
172}
173#[doc = "High Frequency Peripheral Clock Enable Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfperclken0](index.html) module"]
174pub struct HFPERCLKEN0_SPEC;
175impl crate::RegisterSpec for HFPERCLKEN0_SPEC {
176    type Ux = u32;
177}
178#[doc = "`read()` method returns [hfperclken0::R](R) reader structure"]
179impl crate::Readable for HFPERCLKEN0_SPEC {
180    type Reader = R;
181}
182#[doc = "`write(|w| ..)` method takes [hfperclken0::W](W) writer structure"]
183impl crate::Writable for HFPERCLKEN0_SPEC {
184    type Writer = W;
185}
186#[doc = "`reset()` method sets HFPERCLKEN0 to value 0"]
187impl crate::Resettable for HFPERCLKEN0_SPEC {
188    #[inline(always)]
189    fn reset_value() -> Self::Ux {
190        0
191    }
192}
efm32tg108_pac/cmu/hfperclken0.rs

efm32tg108_pac/cmu/
hfperclken0.rs
