efm32tg_pac/efm32tg842/prs/
ch2_ctrl.rs

1#[doc = "Register `CH2_CTRL` reader"]
2pub struct R(crate::R<CH2_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH2_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH2_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH2_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH2_CTRL` writer"]
17pub struct W(crate::W<CH2_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH2_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH2_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH2_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CH2_CTRL_SPEC, u8, u8, 3, O>;
41#[doc = "Field `SOURCESEL` reader - Source Select"]
42pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
43#[doc = "Source Select\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45#[repr(u8)]
46pub enum SOURCESEL_A {
47    #[doc = "0: No source selected"]
48    NONE = 0,
49    #[doc = "1: Voltage Comparator"]
50    VCMP = 1,
51    #[doc = "2: Analog Comparator 0"]
52    ACMP0 = 2,
53    #[doc = "3: Analog Comparator 1"]
54    ACMP1 = 3,
55    #[doc = "6: Digital to Analog Converter 0"]
56    DAC0 = 6,
57    #[doc = "8: Analog to Digital Converter 0"]
58    ADC0 = 8,
59    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
60    USART0 = 16,
61    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
62    USART1 = 17,
63    #[doc = "28: Timer 0"]
64    TIMER0 = 28,
65    #[doc = "29: Timer 1"]
66    TIMER1 = 29,
67    #[doc = "40: Real-Time Counter"]
68    RTC = 40,
69    #[doc = "48: General purpose Input/Output"]
70    GPIOL = 48,
71    #[doc = "49: General purpose Input/Output"]
72    GPIOH = 49,
73    #[doc = "52: Low Energy Timer 0"]
74    LETIMER0 = 52,
75    #[doc = "57: Low Energy Sensor Interface"]
76    LESENSEL = 57,
77    #[doc = "58: Low Energy Sensor Interface"]
78    LESENSEH = 58,
79    #[doc = "59: Low Energy Sensor Interface"]
80    LESENSED = 59,
81}
82impl From<SOURCESEL_A> for u8 {
83    #[inline(always)]
84    fn from(variant: SOURCESEL_A) -> Self {
85        variant as _
86    }
87}
88impl SOURCESEL_R {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub fn variant(&self) -> Option<SOURCESEL_A> {
92        match self.bits {
93            0 => Some(SOURCESEL_A::NONE),
94            1 => Some(SOURCESEL_A::VCMP),
95            2 => Some(SOURCESEL_A::ACMP0),
96            3 => Some(SOURCESEL_A::ACMP1),
97            6 => Some(SOURCESEL_A::DAC0),
98            8 => Some(SOURCESEL_A::ADC0),
99            16 => Some(SOURCESEL_A::USART0),
100            17 => Some(SOURCESEL_A::USART1),
101            28 => Some(SOURCESEL_A::TIMER0),
102            29 => Some(SOURCESEL_A::TIMER1),
103            40 => Some(SOURCESEL_A::RTC),
104            48 => Some(SOURCESEL_A::GPIOL),
105            49 => Some(SOURCESEL_A::GPIOH),
106            52 => Some(SOURCESEL_A::LETIMER0),
107            57 => Some(SOURCESEL_A::LESENSEL),
108            58 => Some(SOURCESEL_A::LESENSEH),
109            59 => Some(SOURCESEL_A::LESENSED),
110            _ => None,
111        }
112    }
113    #[doc = "Checks if the value of the field is `NONE`"]
114    #[inline(always)]
115    pub fn is_none(&self) -> bool {
116        *self == SOURCESEL_A::NONE
117    }
118    #[doc = "Checks if the value of the field is `VCMP`"]
119    #[inline(always)]
120    pub fn is_vcmp(&self) -> bool {
121        *self == SOURCESEL_A::VCMP
122    }
123    #[doc = "Checks if the value of the field is `ACMP0`"]
124    #[inline(always)]
125    pub fn is_acmp0(&self) -> bool {
126        *self == SOURCESEL_A::ACMP0
127    }
128    #[doc = "Checks if the value of the field is `ACMP1`"]
129    #[inline(always)]
130    pub fn is_acmp1(&self) -> bool {
131        *self == SOURCESEL_A::ACMP1
132    }
133    #[doc = "Checks if the value of the field is `DAC0`"]
134    #[inline(always)]
135    pub fn is_dac0(&self) -> bool {
136        *self == SOURCESEL_A::DAC0
137    }
138    #[doc = "Checks if the value of the field is `ADC0`"]
139    #[inline(always)]
140    pub fn is_adc0(&self) -> bool {
141        *self == SOURCESEL_A::ADC0
142    }
143    #[doc = "Checks if the value of the field is `USART0`"]
144    #[inline(always)]
145    pub fn is_usart0(&self) -> bool {
146        *self == SOURCESEL_A::USART0
147    }
148    #[doc = "Checks if the value of the field is `USART1`"]
149    #[inline(always)]
150    pub fn is_usart1(&self) -> bool {
151        *self == SOURCESEL_A::USART1
152    }
153    #[doc = "Checks if the value of the field is `TIMER0`"]
154    #[inline(always)]
155    pub fn is_timer0(&self) -> bool {
156        *self == SOURCESEL_A::TIMER0
157    }
158    #[doc = "Checks if the value of the field is `TIMER1`"]
159    #[inline(always)]
160    pub fn is_timer1(&self) -> bool {
161        *self == SOURCESEL_A::TIMER1
162    }
163    #[doc = "Checks if the value of the field is `RTC`"]
164    #[inline(always)]
165    pub fn is_rtc(&self) -> bool {
166        *self == SOURCESEL_A::RTC
167    }
168    #[doc = "Checks if the value of the field is `GPIOL`"]
169    #[inline(always)]
170    pub fn is_gpiol(&self) -> bool {
171        *self == SOURCESEL_A::GPIOL
172    }
173    #[doc = "Checks if the value of the field is `GPIOH`"]
174    #[inline(always)]
175    pub fn is_gpioh(&self) -> bool {
176        *self == SOURCESEL_A::GPIOH
177    }
178    #[doc = "Checks if the value of the field is `LETIMER0`"]
179    #[inline(always)]
180    pub fn is_letimer0(&self) -> bool {
181        *self == SOURCESEL_A::LETIMER0
182    }
183    #[doc = "Checks if the value of the field is `LESENSEL`"]
184    #[inline(always)]
185    pub fn is_lesensel(&self) -> bool {
186        *self == SOURCESEL_A::LESENSEL
187    }
188    #[doc = "Checks if the value of the field is `LESENSEH`"]
189    #[inline(always)]
190    pub fn is_lesenseh(&self) -> bool {
191        *self == SOURCESEL_A::LESENSEH
192    }
193    #[doc = "Checks if the value of the field is `LESENSED`"]
194    #[inline(always)]
195    pub fn is_lesensed(&self) -> bool {
196        *self == SOURCESEL_A::LESENSED
197    }
198}
199#[doc = "Field `SOURCESEL` writer - Source Select"]
200pub type SOURCESEL_W<'a, const O: u8> =
201    crate::FieldWriter<'a, u32, CH2_CTRL_SPEC, u8, SOURCESEL_A, 6, O>;
202impl<'a, const O: u8> SOURCESEL_W<'a, O> {
203    #[doc = "No source selected"]
204    #[inline(always)]
205    pub fn none(self) -> &'a mut W {
206        self.variant(SOURCESEL_A::NONE)
207    }
208    #[doc = "Voltage Comparator"]
209    #[inline(always)]
210    pub fn vcmp(self) -> &'a mut W {
211        self.variant(SOURCESEL_A::VCMP)
212    }
213    #[doc = "Analog Comparator 0"]
214    #[inline(always)]
215    pub fn acmp0(self) -> &'a mut W {
216        self.variant(SOURCESEL_A::ACMP0)
217    }
218    #[doc = "Analog Comparator 1"]
219    #[inline(always)]
220    pub fn acmp1(self) -> &'a mut W {
221        self.variant(SOURCESEL_A::ACMP1)
222    }
223    #[doc = "Digital to Analog Converter 0"]
224    #[inline(always)]
225    pub fn dac0(self) -> &'a mut W {
226        self.variant(SOURCESEL_A::DAC0)
227    }
228    #[doc = "Analog to Digital Converter 0"]
229    #[inline(always)]
230    pub fn adc0(self) -> &'a mut W {
231        self.variant(SOURCESEL_A::ADC0)
232    }
233    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
234    #[inline(always)]
235    pub fn usart0(self) -> &'a mut W {
236        self.variant(SOURCESEL_A::USART0)
237    }
238    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
239    #[inline(always)]
240    pub fn usart1(self) -> &'a mut W {
241        self.variant(SOURCESEL_A::USART1)
242    }
243    #[doc = "Timer 0"]
244    #[inline(always)]
245    pub fn timer0(self) -> &'a mut W {
246        self.variant(SOURCESEL_A::TIMER0)
247    }
248    #[doc = "Timer 1"]
249    #[inline(always)]
250    pub fn timer1(self) -> &'a mut W {
251        self.variant(SOURCESEL_A::TIMER1)
252    }
253    #[doc = "Real-Time Counter"]
254    #[inline(always)]
255    pub fn rtc(self) -> &'a mut W {
256        self.variant(SOURCESEL_A::RTC)
257    }
258    #[doc = "General purpose Input/Output"]
259    #[inline(always)]
260    pub fn gpiol(self) -> &'a mut W {
261        self.variant(SOURCESEL_A::GPIOL)
262    }
263    #[doc = "General purpose Input/Output"]
264    #[inline(always)]
265    pub fn gpioh(self) -> &'a mut W {
266        self.variant(SOURCESEL_A::GPIOH)
267    }
268    #[doc = "Low Energy Timer 0"]
269    #[inline(always)]
270    pub fn letimer0(self) -> &'a mut W {
271        self.variant(SOURCESEL_A::LETIMER0)
272    }
273    #[doc = "Low Energy Sensor Interface"]
274    #[inline(always)]
275    pub fn lesensel(self) -> &'a mut W {
276        self.variant(SOURCESEL_A::LESENSEL)
277    }
278    #[doc = "Low Energy Sensor Interface"]
279    #[inline(always)]
280    pub fn lesenseh(self) -> &'a mut W {
281        self.variant(SOURCESEL_A::LESENSEH)
282    }
283    #[doc = "Low Energy Sensor Interface"]
284    #[inline(always)]
285    pub fn lesensed(self) -> &'a mut W {
286        self.variant(SOURCESEL_A::LESENSED)
287    }
288}
289#[doc = "Field `EDSEL` reader - Edge Detect Select"]
290pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
291#[doc = "Edge Detect Select\n\nValue on reset: 0"]
292#[derive(Clone, Copy, Debug, PartialEq, Eq)]
293#[repr(u8)]
294pub enum EDSEL_A {
295    #[doc = "0: Signal is left as it is"]
296    OFF = 0,
297    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
298    POSEDGE = 1,
299    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
300    NEGEDGE = 2,
301    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
302    BOTHEDGES = 3,
303}
304impl From<EDSEL_A> for u8 {
305    #[inline(always)]
306    fn from(variant: EDSEL_A) -> Self {
307        variant as _
308    }
309}
310impl EDSEL_R {
311    #[doc = "Get enumerated values variant"]
312    #[inline(always)]
313    pub fn variant(&self) -> EDSEL_A {
314        match self.bits {
315            0 => EDSEL_A::OFF,
316            1 => EDSEL_A::POSEDGE,
317            2 => EDSEL_A::NEGEDGE,
318            3 => EDSEL_A::BOTHEDGES,
319            _ => unreachable!(),
320        }
321    }
322    #[doc = "Checks if the value of the field is `OFF`"]
323    #[inline(always)]
324    pub fn is_off(&self) -> bool {
325        *self == EDSEL_A::OFF
326    }
327    #[doc = "Checks if the value of the field is `POSEDGE`"]
328    #[inline(always)]
329    pub fn is_posedge(&self) -> bool {
330        *self == EDSEL_A::POSEDGE
331    }
332    #[doc = "Checks if the value of the field is `NEGEDGE`"]
333    #[inline(always)]
334    pub fn is_negedge(&self) -> bool {
335        *self == EDSEL_A::NEGEDGE
336    }
337    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
338    #[inline(always)]
339    pub fn is_bothedges(&self) -> bool {
340        *self == EDSEL_A::BOTHEDGES
341    }
342}
343#[doc = "Field `EDSEL` writer - Edge Detect Select"]
344pub type EDSEL_W<'a, const O: u8> =
345    crate::FieldWriterSafe<'a, u32, CH2_CTRL_SPEC, u8, EDSEL_A, 2, O>;
346impl<'a, const O: u8> EDSEL_W<'a, O> {
347    #[doc = "Signal is left as it is"]
348    #[inline(always)]
349    pub fn off(self) -> &'a mut W {
350        self.variant(EDSEL_A::OFF)
351    }
352    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
353    #[inline(always)]
354    pub fn posedge(self) -> &'a mut W {
355        self.variant(EDSEL_A::POSEDGE)
356    }
357    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
358    #[inline(always)]
359    pub fn negedge(self) -> &'a mut W {
360        self.variant(EDSEL_A::NEGEDGE)
361    }
362    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
363    #[inline(always)]
364    pub fn bothedges(self) -> &'a mut W {
365        self.variant(EDSEL_A::BOTHEDGES)
366    }
367}
368#[doc = "Field `ASYNC` reader - Asynchronous reflex"]
369pub type ASYNC_R = crate::BitReader<bool>;
370#[doc = "Field `ASYNC` writer - Asynchronous reflex"]
371pub type ASYNC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH2_CTRL_SPEC, bool, O>;
372impl R {
373    #[doc = "Bits 0:2 - Signal Select"]
374    #[inline(always)]
375    pub fn sigsel(&self) -> SIGSEL_R {
376        SIGSEL_R::new((self.bits & 7) as u8)
377    }
378    #[doc = "Bits 16:21 - Source Select"]
379    #[inline(always)]
380    pub fn sourcesel(&self) -> SOURCESEL_R {
381        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
382    }
383    #[doc = "Bits 24:25 - Edge Detect Select"]
384    #[inline(always)]
385    pub fn edsel(&self) -> EDSEL_R {
386        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
387    }
388    #[doc = "Bit 28 - Asynchronous reflex"]
389    #[inline(always)]
390    pub fn async_(&self) -> ASYNC_R {
391        ASYNC_R::new(((self.bits >> 28) & 1) != 0)
392    }
393}
394impl W {
395    #[doc = "Bits 0:2 - Signal Select"]
396    #[inline(always)]
397    #[must_use]
398    pub fn sigsel(&mut self) -> SIGSEL_W<0> {
399        SIGSEL_W::new(self)
400    }
401    #[doc = "Bits 16:21 - Source Select"]
402    #[inline(always)]
403    #[must_use]
404    pub fn sourcesel(&mut self) -> SOURCESEL_W<16> {
405        SOURCESEL_W::new(self)
406    }
407    #[doc = "Bits 24:25 - Edge Detect Select"]
408    #[inline(always)]
409    #[must_use]
410    pub fn edsel(&mut self) -> EDSEL_W<24> {
411        EDSEL_W::new(self)
412    }
413    #[doc = "Bit 28 - Asynchronous reflex"]
414    #[inline(always)]
415    #[must_use]
416    pub fn async_(&mut self) -> ASYNC_W<28> {
417        ASYNC_W::new(self)
418    }
419    #[doc = "Writes raw bits to the register."]
420    #[inline(always)]
421    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
422        self.0.bits(bits);
423        self
424    }
425}
426#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch2_ctrl](index.html) module"]
427pub struct CH2_CTRL_SPEC;
428impl crate::RegisterSpec for CH2_CTRL_SPEC {
429    type Ux = u32;
430}
431#[doc = "`read()` method returns [ch2_ctrl::R](R) reader structure"]
432impl crate::Readable for CH2_CTRL_SPEC {
433    type Reader = R;
434}
435#[doc = "`write(|w| ..)` method takes [ch2_ctrl::W](W) writer structure"]
436impl crate::Writable for CH2_CTRL_SPEC {
437    type Writer = W;
438    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
439    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
440}
441#[doc = "`reset()` method sets CH2_CTRL to value 0"]
442impl crate::Resettable for CH2_CTRL_SPEC {
443    const RESET_VALUE: Self::Ux = 0;
444}
efm32tg_pac/efm32tg842/prs/ch2_ctrl.rs

efm32tg_pac/efm32tg842/prs/
ch2_ctrl.rs
