efm32pg22_pac/efm32pg22c200/usart1_ns/
ctrlx.rs

1#[doc = "Register `CTRLX` reader"]
2pub struct R(crate::R<CTRLX_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRLX_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRLX_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRLX_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRLX` writer"]
17pub struct W(crate::W<CTRLX_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRLX_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRLX_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRLX_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DBGHALT` reader - Debug halt"]
38pub type DBGHALT_R = crate::BitReader<DBGHALT_A>;
39#[doc = "Debug halt\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum DBGHALT_A {
42    #[doc = "0: Continue to transmit until TX buffer is empty"]
43    DISABLE = 0,
44    #[doc = "1: Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock; otherwise, each single step could transmit multiple frames instead of just transmitting one frame."]
45    ENABLE = 1,
46}
47impl From<DBGHALT_A> for bool {
48    #[inline(always)]
49    fn from(variant: DBGHALT_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl DBGHALT_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> DBGHALT_A {
57        match self.bits {
58            false => DBGHALT_A::DISABLE,
59            true => DBGHALT_A::ENABLE,
60        }
61    }
62    #[doc = "Checks if the value of the field is `DISABLE`"]
63    #[inline(always)]
64    pub fn is_disable(&self) -> bool {
65        *self == DBGHALT_A::DISABLE
66    }
67    #[doc = "Checks if the value of the field is `ENABLE`"]
68    #[inline(always)]
69    pub fn is_enable(&self) -> bool {
70        *self == DBGHALT_A::ENABLE
71    }
72}
73#[doc = "Field `DBGHALT` writer - Debug halt"]
74pub type DBGHALT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLX_SPEC, DBGHALT_A, O>;
75impl<'a, const O: u8> DBGHALT_W<'a, O> {
76    #[doc = "Continue to transmit until TX buffer is empty"]
77    #[inline(always)]
78    pub fn disable(self) -> &'a mut W {
79        self.variant(DBGHALT_A::DISABLE)
80    }
81    #[doc = "Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock; otherwise, each single step could transmit multiple frames instead of just transmitting one frame."]
82    #[inline(always)]
83    pub fn enable(self) -> &'a mut W {
84        self.variant(DBGHALT_A::ENABLE)
85    }
86}
87#[doc = "Field `CTSINV` reader - CTS Pin Inversion"]
88pub type CTSINV_R = crate::BitReader<CTSINV_A>;
89#[doc = "CTS Pin Inversion\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum CTSINV_A {
92    #[doc = "0: The USn_CTS pin is low true"]
93    DISABLE = 0,
94    #[doc = "1: The USn_CTS pin is high true"]
95    ENABLE = 1,
96}
97impl From<CTSINV_A> for bool {
98    #[inline(always)]
99    fn from(variant: CTSINV_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl CTSINV_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> CTSINV_A {
107        match self.bits {
108            false => CTSINV_A::DISABLE,
109            true => CTSINV_A::ENABLE,
110        }
111    }
112    #[doc = "Checks if the value of the field is `DISABLE`"]
113    #[inline(always)]
114    pub fn is_disable(&self) -> bool {
115        *self == CTSINV_A::DISABLE
116    }
117    #[doc = "Checks if the value of the field is `ENABLE`"]
118    #[inline(always)]
119    pub fn is_enable(&self) -> bool {
120        *self == CTSINV_A::ENABLE
121    }
122}
123#[doc = "Field `CTSINV` writer - CTS Pin Inversion"]
124pub type CTSINV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLX_SPEC, CTSINV_A, O>;
125impl<'a, const O: u8> CTSINV_W<'a, O> {
126    #[doc = "The USn_CTS pin is low true"]
127    #[inline(always)]
128    pub fn disable(self) -> &'a mut W {
129        self.variant(CTSINV_A::DISABLE)
130    }
131    #[doc = "The USn_CTS pin is high true"]
132    #[inline(always)]
133    pub fn enable(self) -> &'a mut W {
134        self.variant(CTSINV_A::ENABLE)
135    }
136}
137#[doc = "Field `CTSEN` reader - CTS Function enabled"]
138pub type CTSEN_R = crate::BitReader<CTSEN_A>;
139#[doc = "CTS Function enabled\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum CTSEN_A {
142    #[doc = "0: Ingore CTS"]
143    DISABLE = 0,
144    #[doc = "1: Stop transmitting when CTS is negated"]
145    ENABLE = 1,
146}
147impl From<CTSEN_A> for bool {
148    #[inline(always)]
149    fn from(variant: CTSEN_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl CTSEN_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> CTSEN_A {
157        match self.bits {
158            false => CTSEN_A::DISABLE,
159            true => CTSEN_A::ENABLE,
160        }
161    }
162    #[doc = "Checks if the value of the field is `DISABLE`"]
163    #[inline(always)]
164    pub fn is_disable(&self) -> bool {
165        *self == CTSEN_A::DISABLE
166    }
167    #[doc = "Checks if the value of the field is `ENABLE`"]
168    #[inline(always)]
169    pub fn is_enable(&self) -> bool {
170        *self == CTSEN_A::ENABLE
171    }
172}
173#[doc = "Field `CTSEN` writer - CTS Function enabled"]
174pub type CTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLX_SPEC, CTSEN_A, O>;
175impl<'a, const O: u8> CTSEN_W<'a, O> {
176    #[doc = "Ingore CTS"]
177    #[inline(always)]
178    pub fn disable(self) -> &'a mut W {
179        self.variant(CTSEN_A::DISABLE)
180    }
181    #[doc = "Stop transmitting when CTS is negated"]
182    #[inline(always)]
183    pub fn enable(self) -> &'a mut W {
184        self.variant(CTSEN_A::ENABLE)
185    }
186}
187#[doc = "Field `RTSINV` reader - RTS Pin Inversion"]
188pub type RTSINV_R = crate::BitReader<RTSINV_A>;
189#[doc = "RTS Pin Inversion\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum RTSINV_A {
192    #[doc = "0: The USn_RTS pin is low true"]
193    DISABLE = 0,
194    #[doc = "1: The USn_RTS pin is high true"]
195    ENABLE = 1,
196}
197impl From<RTSINV_A> for bool {
198    #[inline(always)]
199    fn from(variant: RTSINV_A) -> Self {
200        variant as u8 != 0
201    }
202}
203impl RTSINV_R {
204    #[doc = "Get enumerated values variant"]
205    #[inline(always)]
206    pub fn variant(&self) -> RTSINV_A {
207        match self.bits {
208            false => RTSINV_A::DISABLE,
209            true => RTSINV_A::ENABLE,
210        }
211    }
212    #[doc = "Checks if the value of the field is `DISABLE`"]
213    #[inline(always)]
214    pub fn is_disable(&self) -> bool {
215        *self == RTSINV_A::DISABLE
216    }
217    #[doc = "Checks if the value of the field is `ENABLE`"]
218    #[inline(always)]
219    pub fn is_enable(&self) -> bool {
220        *self == RTSINV_A::ENABLE
221    }
222}
223#[doc = "Field `RTSINV` writer - RTS Pin Inversion"]
224pub type RTSINV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLX_SPEC, RTSINV_A, O>;
225impl<'a, const O: u8> RTSINV_W<'a, O> {
226    #[doc = "The USn_RTS pin is low true"]
227    #[inline(always)]
228    pub fn disable(self) -> &'a mut W {
229        self.variant(RTSINV_A::DISABLE)
230    }
231    #[doc = "The USn_RTS pin is high true"]
232    #[inline(always)]
233    pub fn enable(self) -> &'a mut W {
234        self.variant(RTSINV_A::ENABLE)
235    }
236}
237#[doc = "Field `RXPRSEN` reader - PRS RX Enable"]
238pub type RXPRSEN_R = crate::BitReader<bool>;
239#[doc = "Field `RXPRSEN` writer - PRS RX Enable"]
240pub type RXPRSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLX_SPEC, bool, O>;
241#[doc = "Field `CLKPRSEN` reader - PRS CLK Enable"]
242pub type CLKPRSEN_R = crate::BitReader<bool>;
243#[doc = "Field `CLKPRSEN` writer - PRS CLK Enable"]
244pub type CLKPRSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLX_SPEC, bool, O>;
245impl R {
246    #[doc = "Bit 0 - Debug halt"]
247    #[inline(always)]
248    pub fn dbghalt(&self) -> DBGHALT_R {
249        DBGHALT_R::new((self.bits & 1) != 0)
250    }
251    #[doc = "Bit 1 - CTS Pin Inversion"]
252    #[inline(always)]
253    pub fn ctsinv(&self) -> CTSINV_R {
254        CTSINV_R::new(((self.bits >> 1) & 1) != 0)
255    }
256    #[doc = "Bit 2 - CTS Function enabled"]
257    #[inline(always)]
258    pub fn ctsen(&self) -> CTSEN_R {
259        CTSEN_R::new(((self.bits >> 2) & 1) != 0)
260    }
261    #[doc = "Bit 3 - RTS Pin Inversion"]
262    #[inline(always)]
263    pub fn rtsinv(&self) -> RTSINV_R {
264        RTSINV_R::new(((self.bits >> 3) & 1) != 0)
265    }
266    #[doc = "Bit 7 - PRS RX Enable"]
267    #[inline(always)]
268    pub fn rxprsen(&self) -> RXPRSEN_R {
269        RXPRSEN_R::new(((self.bits >> 7) & 1) != 0)
270    }
271    #[doc = "Bit 15 - PRS CLK Enable"]
272    #[inline(always)]
273    pub fn clkprsen(&self) -> CLKPRSEN_R {
274        CLKPRSEN_R::new(((self.bits >> 15) & 1) != 0)
275    }
276}
277impl W {
278    #[doc = "Bit 0 - Debug halt"]
279    #[inline(always)]
280    #[must_use]
281    pub fn dbghalt(&mut self) -> DBGHALT_W<0> {
282        DBGHALT_W::new(self)
283    }
284    #[doc = "Bit 1 - CTS Pin Inversion"]
285    #[inline(always)]
286    #[must_use]
287    pub fn ctsinv(&mut self) -> CTSINV_W<1> {
288        CTSINV_W::new(self)
289    }
290    #[doc = "Bit 2 - CTS Function enabled"]
291    #[inline(always)]
292    #[must_use]
293    pub fn ctsen(&mut self) -> CTSEN_W<2> {
294        CTSEN_W::new(self)
295    }
296    #[doc = "Bit 3 - RTS Pin Inversion"]
297    #[inline(always)]
298    #[must_use]
299    pub fn rtsinv(&mut self) -> RTSINV_W<3> {
300        RTSINV_W::new(self)
301    }
302    #[doc = "Bit 7 - PRS RX Enable"]
303    #[inline(always)]
304    #[must_use]
305    pub fn rxprsen(&mut self) -> RXPRSEN_W<7> {
306        RXPRSEN_W::new(self)
307    }
308    #[doc = "Bit 15 - PRS CLK Enable"]
309    #[inline(always)]
310    #[must_use]
311    pub fn clkprsen(&mut self) -> CLKPRSEN_W<15> {
312        CLKPRSEN_W::new(self)
313    }
314    #[doc = "Writes raw bits to the register."]
315    #[inline(always)]
316    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
317        self.0.bits(bits);
318        self
319    }
320}
321#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlx](index.html) module"]
322pub struct CTRLX_SPEC;
323impl crate::RegisterSpec for CTRLX_SPEC {
324    type Ux = u32;
325}
326#[doc = "`read()` method returns [ctrlx::R](R) reader structure"]
327impl crate::Readable for CTRLX_SPEC {
328    type Reader = R;
329}
330#[doc = "`write(|w| ..)` method takes [ctrlx::W](W) writer structure"]
331impl crate::Writable for CTRLX_SPEC {
332    type Writer = W;
333    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
334    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
335}
336#[doc = "`reset()` method sets CTRLX to value 0"]
337impl crate::Resettable for CTRLX_SPEC {
338    const RESET_VALUE: Self::Ux = 0;
339}
efm32pg22_pac/efm32pg22c200/usart1_ns/ctrlx.rs

efm32pg22_pac/efm32pg22c200/usart1_ns/
ctrlx.rs
