efm32pg22_pac/efm32pg22c200/timer4_ns/
cc0_cfg.rs

1#[doc = "Register `CC0_CFG` reader"]
2pub struct R(crate::R<CC0_CFG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CC0_CFG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CC0_CFG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CC0_CFG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CC0_CFG` writer"]
17pub struct W(crate::W<CC0_CFG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CC0_CFG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CC0_CFG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CC0_CFG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MODE` reader - CC Channel Mode"]
38pub type MODE_R = crate::FieldReader<u8, MODE_A>;
39#[doc = "CC Channel Mode\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum MODE_A {
43    #[doc = "0: Compare/Capture channel turned off"]
44    OFF = 0,
45    #[doc = "1: Input Capture"]
46    INPUTCAPTURE = 1,
47    #[doc = "2: Output Compare"]
48    OUTPUTCOMPARE = 2,
49    #[doc = "3: Pulse-Width Modulation"]
50    PWM = 3,
51}
52impl From<MODE_A> for u8 {
53    #[inline(always)]
54    fn from(variant: MODE_A) -> Self {
55        variant as _
56    }
57}
58impl MODE_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> MODE_A {
62        match self.bits {
63            0 => MODE_A::OFF,
64            1 => MODE_A::INPUTCAPTURE,
65            2 => MODE_A::OUTPUTCOMPARE,
66            3 => MODE_A::PWM,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `OFF`"]
71    #[inline(always)]
72    pub fn is_off(&self) -> bool {
73        *self == MODE_A::OFF
74    }
75    #[doc = "Checks if the value of the field is `INPUTCAPTURE`"]
76    #[inline(always)]
77    pub fn is_inputcapture(&self) -> bool {
78        *self == MODE_A::INPUTCAPTURE
79    }
80    #[doc = "Checks if the value of the field is `OUTPUTCOMPARE`"]
81    #[inline(always)]
82    pub fn is_outputcompare(&self) -> bool {
83        *self == MODE_A::OUTPUTCOMPARE
84    }
85    #[doc = "Checks if the value of the field is `PWM`"]
86    #[inline(always)]
87    pub fn is_pwm(&self) -> bool {
88        *self == MODE_A::PWM
89    }
90}
91#[doc = "Field `MODE` writer - CC Channel Mode"]
92pub type MODE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CC0_CFG_SPEC, u8, MODE_A, 2, O>;
93impl<'a, const O: u8> MODE_W<'a, O> {
94    #[doc = "Compare/Capture channel turned off"]
95    #[inline(always)]
96    pub fn off(self) -> &'a mut W {
97        self.variant(MODE_A::OFF)
98    }
99    #[doc = "Input Capture"]
100    #[inline(always)]
101    pub fn inputcapture(self) -> &'a mut W {
102        self.variant(MODE_A::INPUTCAPTURE)
103    }
104    #[doc = "Output Compare"]
105    #[inline(always)]
106    pub fn outputcompare(self) -> &'a mut W {
107        self.variant(MODE_A::OUTPUTCOMPARE)
108    }
109    #[doc = "Pulse-Width Modulation"]
110    #[inline(always)]
111    pub fn pwm(self) -> &'a mut W {
112        self.variant(MODE_A::PWM)
113    }
114}
115#[doc = "Field `COIST` reader - Compare Output Initial State"]
116pub type COIST_R = crate::BitReader<bool>;
117#[doc = "Field `COIST` writer - Compare Output Initial State"]
118pub type COIST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CC0_CFG_SPEC, bool, O>;
119#[doc = "Field `INSEL` reader - Input Selection"]
120pub type INSEL_R = crate::FieldReader<u8, INSEL_A>;
121#[doc = "Input Selection\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq, Eq)]
123#[repr(u8)]
124pub enum INSEL_A {
125    #[doc = "0: TIMERnCCx pin is selected"]
126    PIN = 0,
127    #[doc = "1: Synchornous PRS selected"]
128    PRSSYNC = 1,
129    #[doc = "2: Asynchronous Level PRS selected"]
130    PRSASYNCLEVEL = 2,
131    #[doc = "3: Asynchronous Pulse PRS selected"]
132    PRSASYNCPULSE = 3,
133}
134impl From<INSEL_A> for u8 {
135    #[inline(always)]
136    fn from(variant: INSEL_A) -> Self {
137        variant as _
138    }
139}
140impl INSEL_R {
141    #[doc = "Get enumerated values variant"]
142    #[inline(always)]
143    pub fn variant(&self) -> INSEL_A {
144        match self.bits {
145            0 => INSEL_A::PIN,
146            1 => INSEL_A::PRSSYNC,
147            2 => INSEL_A::PRSASYNCLEVEL,
148            3 => INSEL_A::PRSASYNCPULSE,
149            _ => unreachable!(),
150        }
151    }
152    #[doc = "Checks if the value of the field is `PIN`"]
153    #[inline(always)]
154    pub fn is_pin(&self) -> bool {
155        *self == INSEL_A::PIN
156    }
157    #[doc = "Checks if the value of the field is `PRSSYNC`"]
158    #[inline(always)]
159    pub fn is_prssync(&self) -> bool {
160        *self == INSEL_A::PRSSYNC
161    }
162    #[doc = "Checks if the value of the field is `PRSASYNCLEVEL`"]
163    #[inline(always)]
164    pub fn is_prsasynclevel(&self) -> bool {
165        *self == INSEL_A::PRSASYNCLEVEL
166    }
167    #[doc = "Checks if the value of the field is `PRSASYNCPULSE`"]
168    #[inline(always)]
169    pub fn is_prsasyncpulse(&self) -> bool {
170        *self == INSEL_A::PRSASYNCPULSE
171    }
172}
173#[doc = "Field `INSEL` writer - Input Selection"]
174pub type INSEL_W<'a, const O: u8> =
175    crate::FieldWriterSafe<'a, u32, CC0_CFG_SPEC, u8, INSEL_A, 2, O>;
176impl<'a, const O: u8> INSEL_W<'a, O> {
177    #[doc = "TIMERnCCx pin is selected"]
178    #[inline(always)]
179    pub fn pin(self) -> &'a mut W {
180        self.variant(INSEL_A::PIN)
181    }
182    #[doc = "Synchornous PRS selected"]
183    #[inline(always)]
184    pub fn prssync(self) -> &'a mut W {
185        self.variant(INSEL_A::PRSSYNC)
186    }
187    #[doc = "Asynchronous Level PRS selected"]
188    #[inline(always)]
189    pub fn prsasynclevel(self) -> &'a mut W {
190        self.variant(INSEL_A::PRSASYNCLEVEL)
191    }
192    #[doc = "Asynchronous Pulse PRS selected"]
193    #[inline(always)]
194    pub fn prsasyncpulse(self) -> &'a mut W {
195        self.variant(INSEL_A::PRSASYNCPULSE)
196    }
197}
198#[doc = "Field `PRSCONF` reader - PRS Configuration"]
199pub type PRSCONF_R = crate::BitReader<PRSCONF_A>;
200#[doc = "PRS Configuration\n\nValue on reset: 0"]
201#[derive(Clone, Copy, Debug, PartialEq, Eq)]
202pub enum PRSCONF_A {
203    #[doc = "0: Each CC event will generate a one EM01GRPACLK cycle high pulse"]
204    PULSE = 0,
205    #[doc = "1: The PRS channel will follow CC out"]
206    LEVEL = 1,
207}
208impl From<PRSCONF_A> for bool {
209    #[inline(always)]
210    fn from(variant: PRSCONF_A) -> Self {
211        variant as u8 != 0
212    }
213}
214impl PRSCONF_R {
215    #[doc = "Get enumerated values variant"]
216    #[inline(always)]
217    pub fn variant(&self) -> PRSCONF_A {
218        match self.bits {
219            false => PRSCONF_A::PULSE,
220            true => PRSCONF_A::LEVEL,
221        }
222    }
223    #[doc = "Checks if the value of the field is `PULSE`"]
224    #[inline(always)]
225    pub fn is_pulse(&self) -> bool {
226        *self == PRSCONF_A::PULSE
227    }
228    #[doc = "Checks if the value of the field is `LEVEL`"]
229    #[inline(always)]
230    pub fn is_level(&self) -> bool {
231        *self == PRSCONF_A::LEVEL
232    }
233}
234#[doc = "Field `PRSCONF` writer - PRS Configuration"]
235pub type PRSCONF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CC0_CFG_SPEC, PRSCONF_A, O>;
236impl<'a, const O: u8> PRSCONF_W<'a, O> {
237    #[doc = "Each CC event will generate a one EM01GRPACLK cycle high pulse"]
238    #[inline(always)]
239    pub fn pulse(self) -> &'a mut W {
240        self.variant(PRSCONF_A::PULSE)
241    }
242    #[doc = "The PRS channel will follow CC out"]
243    #[inline(always)]
244    pub fn level(self) -> &'a mut W {
245        self.variant(PRSCONF_A::LEVEL)
246    }
247}
248#[doc = "Field `FILT` reader - Digital Filter"]
249pub type FILT_R = crate::BitReader<FILT_A>;
250#[doc = "Digital Filter\n\nValue on reset: 0"]
251#[derive(Clone, Copy, Debug, PartialEq, Eq)]
252pub enum FILT_A {
253    #[doc = "0: Digital Filter Disabled"]
254    DISABLE = 0,
255    #[doc = "1: Digital Filter Enabled"]
256    ENABLE = 1,
257}
258impl From<FILT_A> for bool {
259    #[inline(always)]
260    fn from(variant: FILT_A) -> Self {
261        variant as u8 != 0
262    }
263}
264impl FILT_R {
265    #[doc = "Get enumerated values variant"]
266    #[inline(always)]
267    pub fn variant(&self) -> FILT_A {
268        match self.bits {
269            false => FILT_A::DISABLE,
270            true => FILT_A::ENABLE,
271        }
272    }
273    #[doc = "Checks if the value of the field is `DISABLE`"]
274    #[inline(always)]
275    pub fn is_disable(&self) -> bool {
276        *self == FILT_A::DISABLE
277    }
278    #[doc = "Checks if the value of the field is `ENABLE`"]
279    #[inline(always)]
280    pub fn is_enable(&self) -> bool {
281        *self == FILT_A::ENABLE
282    }
283}
284#[doc = "Field `FILT` writer - Digital Filter"]
285pub type FILT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CC0_CFG_SPEC, FILT_A, O>;
286impl<'a, const O: u8> FILT_W<'a, O> {
287    #[doc = "Digital Filter Disabled"]
288    #[inline(always)]
289    pub fn disable(self) -> &'a mut W {
290        self.variant(FILT_A::DISABLE)
291    }
292    #[doc = "Digital Filter Enabled"]
293    #[inline(always)]
294    pub fn enable(self) -> &'a mut W {
295        self.variant(FILT_A::ENABLE)
296    }
297}
298#[doc = "Field `ICFWL` reader - Input Capture FIFO watermark level"]
299pub type ICFWL_R = crate::BitReader<bool>;
300#[doc = "Field `ICFWL` writer - Input Capture FIFO watermark level"]
301pub type ICFWL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CC0_CFG_SPEC, bool, O>;
302impl R {
303    #[doc = "Bits 0:1 - CC Channel Mode"]
304    #[inline(always)]
305    pub fn mode(&self) -> MODE_R {
306        MODE_R::new((self.bits & 3) as u8)
307    }
308    #[doc = "Bit 4 - Compare Output Initial State"]
309    #[inline(always)]
310    pub fn coist(&self) -> COIST_R {
311        COIST_R::new(((self.bits >> 4) & 1) != 0)
312    }
313    #[doc = "Bits 17:18 - Input Selection"]
314    #[inline(always)]
315    pub fn insel(&self) -> INSEL_R {
316        INSEL_R::new(((self.bits >> 17) & 3) as u8)
317    }
318    #[doc = "Bit 19 - PRS Configuration"]
319    #[inline(always)]
320    pub fn prsconf(&self) -> PRSCONF_R {
321        PRSCONF_R::new(((self.bits >> 19) & 1) != 0)
322    }
323    #[doc = "Bit 20 - Digital Filter"]
324    #[inline(always)]
325    pub fn filt(&self) -> FILT_R {
326        FILT_R::new(((self.bits >> 20) & 1) != 0)
327    }
328    #[doc = "Bit 21 - Input Capture FIFO watermark level"]
329    #[inline(always)]
330    pub fn icfwl(&self) -> ICFWL_R {
331        ICFWL_R::new(((self.bits >> 21) & 1) != 0)
332    }
333}
334impl W {
335    #[doc = "Bits 0:1 - CC Channel Mode"]
336    #[inline(always)]
337    #[must_use]
338    pub fn mode(&mut self) -> MODE_W<0> {
339        MODE_W::new(self)
340    }
341    #[doc = "Bit 4 - Compare Output Initial State"]
342    #[inline(always)]
343    #[must_use]
344    pub fn coist(&mut self) -> COIST_W<4> {
345        COIST_W::new(self)
346    }
347    #[doc = "Bits 17:18 - Input Selection"]
348    #[inline(always)]
349    #[must_use]
350    pub fn insel(&mut self) -> INSEL_W<17> {
351        INSEL_W::new(self)
352    }
353    #[doc = "Bit 19 - PRS Configuration"]
354    #[inline(always)]
355    #[must_use]
356    pub fn prsconf(&mut self) -> PRSCONF_W<19> {
357        PRSCONF_W::new(self)
358    }
359    #[doc = "Bit 20 - Digital Filter"]
360    #[inline(always)]
361    #[must_use]
362    pub fn filt(&mut self) -> FILT_W<20> {
363        FILT_W::new(self)
364    }
365    #[doc = "Bit 21 - Input Capture FIFO watermark level"]
366    #[inline(always)]
367    #[must_use]
368    pub fn icfwl(&mut self) -> ICFWL_W<21> {
369        ICFWL_W::new(self)
370    }
371    #[doc = "Writes raw bits to the register."]
372    #[inline(always)]
373    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
374        self.0.bits(bits);
375        self
376    }
377}
378#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc0_cfg](index.html) module"]
379pub struct CC0_CFG_SPEC;
380impl crate::RegisterSpec for CC0_CFG_SPEC {
381    type Ux = u32;
382}
383#[doc = "`read()` method returns [cc0_cfg::R](R) reader structure"]
384impl crate::Readable for CC0_CFG_SPEC {
385    type Reader = R;
386}
387#[doc = "`write(|w| ..)` method takes [cc0_cfg::W](W) writer structure"]
388impl crate::Writable for CC0_CFG_SPEC {
389    type Writer = W;
390    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
391    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
392}
393#[doc = "`reset()` method sets CC0_CFG to value 0"]
394impl crate::Resettable for CC0_CFG_SPEC {
395    const RESET_VALUE: Self::Ux = 0;
396}
efm32pg22_pac/efm32pg22c200/timer4_ns/cc0_cfg.rs

efm32pg22_pac/efm32pg22c200/timer4_ns/
cc0_cfg.rs
