efm32pg22_pac/efm32pg22c200/timer0_s/
ien.rs

1#[doc = "Register `IEN` reader"]
2pub struct R(crate::R<IEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `IEN` writer"]
17pub struct W(crate::W<IEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `OF` reader - Overflow Interrupt Enable"]
38pub type OF_R = crate::BitReader<bool>;
39#[doc = "Field `OF` writer - Overflow Interrupt Enable"]
40pub type OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
41#[doc = "Field `UF` reader - Underflow Interrupt Enable"]
42pub type UF_R = crate::BitReader<bool>;
43#[doc = "Field `UF` writer - Underflow Interrupt Enable"]
44pub type UF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
45#[doc = "Field `DIRCHG` reader - Direction Change Detect Interrupt Enable"]
46pub type DIRCHG_R = crate::BitReader<bool>;
47#[doc = "Field `DIRCHG` writer - Direction Change Detect Interrupt Enable"]
48pub type DIRCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
49#[doc = "Field `CC0` reader - CC0 Interrupt Enable"]
50pub type CC0_R = crate::BitReader<bool>;
51#[doc = "Field `CC0` writer - CC0 Interrupt Enable"]
52pub type CC0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
53#[doc = "Field `CC1` reader - CC1 Interrupt Enable"]
54pub type CC1_R = crate::BitReader<bool>;
55#[doc = "Field `CC1` writer - CC1 Interrupt Enable"]
56pub type CC1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
57#[doc = "Field `CC2` reader - CC2 Interrupt Enable"]
58pub type CC2_R = crate::BitReader<bool>;
59#[doc = "Field `CC2` writer - CC2 Interrupt Enable"]
60pub type CC2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
61#[doc = "Field `ICFWLFULL0` reader - ICFWLFULL0 Interrupt Enable"]
62pub type ICFWLFULL0_R = crate::BitReader<bool>;
63#[doc = "Field `ICFWLFULL0` writer - ICFWLFULL0 Interrupt Enable"]
64pub type ICFWLFULL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
65#[doc = "Field `ICFWLFULL1` reader - ICFWLFULL1 Interrupt Enable"]
66pub type ICFWLFULL1_R = crate::BitReader<bool>;
67#[doc = "Field `ICFWLFULL1` writer - ICFWLFULL1 Interrupt Enable"]
68pub type ICFWLFULL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
69#[doc = "Field `ICFWLFULL2` reader - ICFWLFULL2 Interrupt Enable"]
70pub type ICFWLFULL2_R = crate::BitReader<bool>;
71#[doc = "Field `ICFWLFULL2` writer - ICFWLFULL2 Interrupt Enable"]
72pub type ICFWLFULL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
73#[doc = "Field `ICFOF0` reader - ICFOF0 Interrupt Enable"]
74pub type ICFOF0_R = crate::BitReader<bool>;
75#[doc = "Field `ICFOF0` writer - ICFOF0 Interrupt Enable"]
76pub type ICFOF0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
77#[doc = "Field `ICFOF1` reader - ICFOF1 Interrupt Enable"]
78pub type ICFOF1_R = crate::BitReader<bool>;
79#[doc = "Field `ICFOF1` writer - ICFOF1 Interrupt Enable"]
80pub type ICFOF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
81#[doc = "Field `ICFOF2` reader - ICFOF2 Interrupt Enable"]
82pub type ICFOF2_R = crate::BitReader<bool>;
83#[doc = "Field `ICFOF2` writer - ICFOF2 Interrupt Enable"]
84pub type ICFOF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
85#[doc = "Field `ICFUF0` reader - ICFUF0 Interrupt Enable"]
86pub type ICFUF0_R = crate::BitReader<bool>;
87#[doc = "Field `ICFUF0` writer - ICFUF0 Interrupt Enable"]
88pub type ICFUF0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
89#[doc = "Field `ICFUF1` reader - ICFUF1 Interrupt Enable"]
90pub type ICFUF1_R = crate::BitReader<bool>;
91#[doc = "Field `ICFUF1` writer - ICFUF1 Interrupt Enable"]
92pub type ICFUF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
93#[doc = "Field `ICFUF2` reader - ICFUF2 Interrupt Enable"]
94pub type ICFUF2_R = crate::BitReader<bool>;
95#[doc = "Field `ICFUF2` writer - ICFUF2 Interrupt Enable"]
96pub type ICFUF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
97impl R {
98    #[doc = "Bit 0 - Overflow Interrupt Enable"]
99    #[inline(always)]
100    pub fn of(&self) -> OF_R {
101        OF_R::new((self.bits & 1) != 0)
102    }
103    #[doc = "Bit 1 - Underflow Interrupt Enable"]
104    #[inline(always)]
105    pub fn uf(&self) -> UF_R {
106        UF_R::new(((self.bits >> 1) & 1) != 0)
107    }
108    #[doc = "Bit 2 - Direction Change Detect Interrupt Enable"]
109    #[inline(always)]
110    pub fn dirchg(&self) -> DIRCHG_R {
111        DIRCHG_R::new(((self.bits >> 2) & 1) != 0)
112    }
113    #[doc = "Bit 4 - CC0 Interrupt Enable"]
114    #[inline(always)]
115    pub fn cc0(&self) -> CC0_R {
116        CC0_R::new(((self.bits >> 4) & 1) != 0)
117    }
118    #[doc = "Bit 5 - CC1 Interrupt Enable"]
119    #[inline(always)]
120    pub fn cc1(&self) -> CC1_R {
121        CC1_R::new(((self.bits >> 5) & 1) != 0)
122    }
123    #[doc = "Bit 6 - CC2 Interrupt Enable"]
124    #[inline(always)]
125    pub fn cc2(&self) -> CC2_R {
126        CC2_R::new(((self.bits >> 6) & 1) != 0)
127    }
128    #[doc = "Bit 16 - ICFWLFULL0 Interrupt Enable"]
129    #[inline(always)]
130    pub fn icfwlfull0(&self) -> ICFWLFULL0_R {
131        ICFWLFULL0_R::new(((self.bits >> 16) & 1) != 0)
132    }
133    #[doc = "Bit 17 - ICFWLFULL1 Interrupt Enable"]
134    #[inline(always)]
135    pub fn icfwlfull1(&self) -> ICFWLFULL1_R {
136        ICFWLFULL1_R::new(((self.bits >> 17) & 1) != 0)
137    }
138    #[doc = "Bit 18 - ICFWLFULL2 Interrupt Enable"]
139    #[inline(always)]
140    pub fn icfwlfull2(&self) -> ICFWLFULL2_R {
141        ICFWLFULL2_R::new(((self.bits >> 18) & 1) != 0)
142    }
143    #[doc = "Bit 20 - ICFOF0 Interrupt Enable"]
144    #[inline(always)]
145    pub fn icfof0(&self) -> ICFOF0_R {
146        ICFOF0_R::new(((self.bits >> 20) & 1) != 0)
147    }
148    #[doc = "Bit 21 - ICFOF1 Interrupt Enable"]
149    #[inline(always)]
150    pub fn icfof1(&self) -> ICFOF1_R {
151        ICFOF1_R::new(((self.bits >> 21) & 1) != 0)
152    }
153    #[doc = "Bit 22 - ICFOF2 Interrupt Enable"]
154    #[inline(always)]
155    pub fn icfof2(&self) -> ICFOF2_R {
156        ICFOF2_R::new(((self.bits >> 22) & 1) != 0)
157    }
158    #[doc = "Bit 24 - ICFUF0 Interrupt Enable"]
159    #[inline(always)]
160    pub fn icfuf0(&self) -> ICFUF0_R {
161        ICFUF0_R::new(((self.bits >> 24) & 1) != 0)
162    }
163    #[doc = "Bit 25 - ICFUF1 Interrupt Enable"]
164    #[inline(always)]
165    pub fn icfuf1(&self) -> ICFUF1_R {
166        ICFUF1_R::new(((self.bits >> 25) & 1) != 0)
167    }
168    #[doc = "Bit 26 - ICFUF2 Interrupt Enable"]
169    #[inline(always)]
170    pub fn icfuf2(&self) -> ICFUF2_R {
171        ICFUF2_R::new(((self.bits >> 26) & 1) != 0)
172    }
173}
174impl W {
175    #[doc = "Bit 0 - Overflow Interrupt Enable"]
176    #[inline(always)]
177    #[must_use]
178    pub fn of(&mut self) -> OF_W<0> {
179        OF_W::new(self)
180    }
181    #[doc = "Bit 1 - Underflow Interrupt Enable"]
182    #[inline(always)]
183    #[must_use]
184    pub fn uf(&mut self) -> UF_W<1> {
185        UF_W::new(self)
186    }
187    #[doc = "Bit 2 - Direction Change Detect Interrupt Enable"]
188    #[inline(always)]
189    #[must_use]
190    pub fn dirchg(&mut self) -> DIRCHG_W<2> {
191        DIRCHG_W::new(self)
192    }
193    #[doc = "Bit 4 - CC0 Interrupt Enable"]
194    #[inline(always)]
195    #[must_use]
196    pub fn cc0(&mut self) -> CC0_W<4> {
197        CC0_W::new(self)
198    }
199    #[doc = "Bit 5 - CC1 Interrupt Enable"]
200    #[inline(always)]
201    #[must_use]
202    pub fn cc1(&mut self) -> CC1_W<5> {
203        CC1_W::new(self)
204    }
205    #[doc = "Bit 6 - CC2 Interrupt Enable"]
206    #[inline(always)]
207    #[must_use]
208    pub fn cc2(&mut self) -> CC2_W<6> {
209        CC2_W::new(self)
210    }
211    #[doc = "Bit 16 - ICFWLFULL0 Interrupt Enable"]
212    #[inline(always)]
213    #[must_use]
214    pub fn icfwlfull0(&mut self) -> ICFWLFULL0_W<16> {
215        ICFWLFULL0_W::new(self)
216    }
217    #[doc = "Bit 17 - ICFWLFULL1 Interrupt Enable"]
218    #[inline(always)]
219    #[must_use]
220    pub fn icfwlfull1(&mut self) -> ICFWLFULL1_W<17> {
221        ICFWLFULL1_W::new(self)
222    }
223    #[doc = "Bit 18 - ICFWLFULL2 Interrupt Enable"]
224    #[inline(always)]
225    #[must_use]
226    pub fn icfwlfull2(&mut self) -> ICFWLFULL2_W<18> {
227        ICFWLFULL2_W::new(self)
228    }
229    #[doc = "Bit 20 - ICFOF0 Interrupt Enable"]
230    #[inline(always)]
231    #[must_use]
232    pub fn icfof0(&mut self) -> ICFOF0_W<20> {
233        ICFOF0_W::new(self)
234    }
235    #[doc = "Bit 21 - ICFOF1 Interrupt Enable"]
236    #[inline(always)]
237    #[must_use]
238    pub fn icfof1(&mut self) -> ICFOF1_W<21> {
239        ICFOF1_W::new(self)
240    }
241    #[doc = "Bit 22 - ICFOF2 Interrupt Enable"]
242    #[inline(always)]
243    #[must_use]
244    pub fn icfof2(&mut self) -> ICFOF2_W<22> {
245        ICFOF2_W::new(self)
246    }
247    #[doc = "Bit 24 - ICFUF0 Interrupt Enable"]
248    #[inline(always)]
249    #[must_use]
250    pub fn icfuf0(&mut self) -> ICFUF0_W<24> {
251        ICFUF0_W::new(self)
252    }
253    #[doc = "Bit 25 - ICFUF1 Interrupt Enable"]
254    #[inline(always)]
255    #[must_use]
256    pub fn icfuf1(&mut self) -> ICFUF1_W<25> {
257        ICFUF1_W::new(self)
258    }
259    #[doc = "Bit 26 - ICFUF2 Interrupt Enable"]
260    #[inline(always)]
261    #[must_use]
262    pub fn icfuf2(&mut self) -> ICFUF2_W<26> {
263        ICFUF2_W::new(self)
264    }
265    #[doc = "Writes raw bits to the register."]
266    #[inline(always)]
267    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
268        self.0.bits(bits);
269        self
270    }
271}
272#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ien](index.html) module"]
273pub struct IEN_SPEC;
274impl crate::RegisterSpec for IEN_SPEC {
275    type Ux = u32;
276}
277#[doc = "`read()` method returns [ien::R](R) reader structure"]
278impl crate::Readable for IEN_SPEC {
279    type Reader = R;
280}
281#[doc = "`write(|w| ..)` method takes [ien::W](W) writer structure"]
282impl crate::Writable for IEN_SPEC {
283    type Writer = W;
284    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
285    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
286}
287#[doc = "`reset()` method sets IEN to value 0"]
288impl crate::Resettable for IEN_SPEC {
289    const RESET_VALUE: Self::Ux = 0;
290}
efm32pg22_pac/efm32pg22c200/timer0_s/ien.rs

efm32pg22_pac/efm32pg22c200/timer0_s/
ien.rs
