efm32pg22_pac/efm32pg22c200/prs_s/
sync_ch0_ctrl.rs

1#[doc = "Register `SYNC_CH0_CTRL` reader"]
2pub struct R(crate::R<SYNC_CH0_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SYNC_CH0_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SYNC_CH0_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SYNC_CH0_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SYNC_CH0_CTRL` writer"]
17pub struct W(crate::W<SYNC_CH0_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SYNC_CH0_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SYNC_CH0_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SYNC_CH0_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SYNC_CH0_CTRL_SPEC, u8, u8, 3, O>;
41#[doc = "Field `SOURCESEL` reader - Source Select"]
42pub type SOURCESEL_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `SOURCESEL` writer - Source Select"]
44pub type SOURCESEL_W<'a, const O: u8> =
45    crate::FieldWriter<'a, u32, SYNC_CH0_CTRL_SPEC, u8, u8, 7, O>;
46impl R {
47    #[doc = "Bits 0:2 - Signal Select"]
48    #[inline(always)]
49    pub fn sigsel(&self) -> SIGSEL_R {
50        SIGSEL_R::new((self.bits & 7) as u8)
51    }
52    #[doc = "Bits 8:14 - Source Select"]
53    #[inline(always)]
54    pub fn sourcesel(&self) -> SOURCESEL_R {
55        SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
56    }
57}
58impl W {
59    #[doc = "Bits 0:2 - Signal Select"]
60    #[inline(always)]
61    #[must_use]
62    pub fn sigsel(&mut self) -> SIGSEL_W<0> {
63        SIGSEL_W::new(self)
64    }
65    #[doc = "Bits 8:14 - Source Select"]
66    #[inline(always)]
67    #[must_use]
68    pub fn sourcesel(&mut self) -> SOURCESEL_W<8> {
69        SOURCESEL_W::new(self)
70    }
71    #[doc = "Writes raw bits to the register."]
72    #[inline(always)]
73    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
74        self.0.bits(bits);
75        self
76    }
77}
78#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sync_ch0_ctrl](index.html) module"]
79pub struct SYNC_CH0_CTRL_SPEC;
80impl crate::RegisterSpec for SYNC_CH0_CTRL_SPEC {
81    type Ux = u32;
82}
83#[doc = "`read()` method returns [sync_ch0_ctrl::R](R) reader structure"]
84impl crate::Readable for SYNC_CH0_CTRL_SPEC {
85    type Reader = R;
86}
87#[doc = "`write(|w| ..)` method takes [sync_ch0_ctrl::W](W) writer structure"]
88impl crate::Writable for SYNC_CH0_CTRL_SPEC {
89    type Writer = W;
90    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
91    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
92}
93#[doc = "`reset()` method sets SYNC_CH0_CTRL to value 0"]
94impl crate::Resettable for SYNC_CH0_CTRL_SPEC {
95    const RESET_VALUE: Self::Ux = 0;
96}
efm32pg22_pac/efm32pg22c200/prs_s/sync_ch0_ctrl.rs

efm32pg22_pac/efm32pg22c200/prs_s/
sync_ch0_ctrl.rs
