efm32pg22_pac/efm32pg22c200/ldma_s/
synchwsel.rs

1#[doc = "Register `SYNCHWSEL` reader"]
2pub struct R(crate::R<SYNCHWSEL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SYNCHWSEL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SYNCHWSEL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SYNCHWSEL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SYNCHWSEL` writer"]
17pub struct W(crate::W<SYNCHWSEL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SYNCHWSEL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SYNCHWSEL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SYNCHWSEL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SYNCSETEDGE` reader - Hardware Sync Trigger Set Edge Select"]
38pub type SYNCSETEDGE_R = crate::FieldReader<u8, SYNCSETEDGE_A>;
39#[doc = "Hardware Sync Trigger Set Edge Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum SYNCSETEDGE_A {
43    #[doc = "0: Use rising edge detection"]
44    RISE = 0,
45    #[doc = "1: Use falling edge detection"]
46    FALL = 1,
47}
48impl From<SYNCSETEDGE_A> for u8 {
49    #[inline(always)]
50    fn from(variant: SYNCSETEDGE_A) -> Self {
51        variant as _
52    }
53}
54impl SYNCSETEDGE_R {
55    #[doc = "Get enumerated values variant"]
56    #[inline(always)]
57    pub fn variant(&self) -> Option<SYNCSETEDGE_A> {
58        match self.bits {
59            0 => Some(SYNCSETEDGE_A::RISE),
60            1 => Some(SYNCSETEDGE_A::FALL),
61            _ => None,
62        }
63    }
64    #[doc = "Checks if the value of the field is `RISE`"]
65    #[inline(always)]
66    pub fn is_rise(&self) -> bool {
67        *self == SYNCSETEDGE_A::RISE
68    }
69    #[doc = "Checks if the value of the field is `FALL`"]
70    #[inline(always)]
71    pub fn is_fall(&self) -> bool {
72        *self == SYNCSETEDGE_A::FALL
73    }
74}
75#[doc = "Field `SYNCSETEDGE` writer - Hardware Sync Trigger Set Edge Select"]
76pub type SYNCSETEDGE_W<'a, const O: u8> =
77    crate::FieldWriter<'a, u32, SYNCHWSEL_SPEC, u8, SYNCSETEDGE_A, 8, O>;
78impl<'a, const O: u8> SYNCSETEDGE_W<'a, O> {
79    #[doc = "Use rising edge detection"]
80    #[inline(always)]
81    pub fn rise(self) -> &'a mut W {
82        self.variant(SYNCSETEDGE_A::RISE)
83    }
84    #[doc = "Use falling edge detection"]
85    #[inline(always)]
86    pub fn fall(self) -> &'a mut W {
87        self.variant(SYNCSETEDGE_A::FALL)
88    }
89}
90#[doc = "Field `SYNCCLREDGE` reader - Hardware Sync Trigger Clear Edge Select"]
91pub type SYNCCLREDGE_R = crate::FieldReader<u8, SYNCCLREDGE_A>;
92#[doc = "Hardware Sync Trigger Clear Edge Select\n\nValue on reset: 0"]
93#[derive(Clone, Copy, Debug, PartialEq, Eq)]
94#[repr(u8)]
95pub enum SYNCCLREDGE_A {
96    #[doc = "0: Use rising edge detection"]
97    RISE = 0,
98    #[doc = "1: Use falling edge detection"]
99    FALL = 1,
100}
101impl From<SYNCCLREDGE_A> for u8 {
102    #[inline(always)]
103    fn from(variant: SYNCCLREDGE_A) -> Self {
104        variant as _
105    }
106}
107impl SYNCCLREDGE_R {
108    #[doc = "Get enumerated values variant"]
109    #[inline(always)]
110    pub fn variant(&self) -> Option<SYNCCLREDGE_A> {
111        match self.bits {
112            0 => Some(SYNCCLREDGE_A::RISE),
113            1 => Some(SYNCCLREDGE_A::FALL),
114            _ => None,
115        }
116    }
117    #[doc = "Checks if the value of the field is `RISE`"]
118    #[inline(always)]
119    pub fn is_rise(&self) -> bool {
120        *self == SYNCCLREDGE_A::RISE
121    }
122    #[doc = "Checks if the value of the field is `FALL`"]
123    #[inline(always)]
124    pub fn is_fall(&self) -> bool {
125        *self == SYNCCLREDGE_A::FALL
126    }
127}
128#[doc = "Field `SYNCCLREDGE` writer - Hardware Sync Trigger Clear Edge Select"]
129pub type SYNCCLREDGE_W<'a, const O: u8> =
130    crate::FieldWriter<'a, u32, SYNCHWSEL_SPEC, u8, SYNCCLREDGE_A, 8, O>;
131impl<'a, const O: u8> SYNCCLREDGE_W<'a, O> {
132    #[doc = "Use rising edge detection"]
133    #[inline(always)]
134    pub fn rise(self) -> &'a mut W {
135        self.variant(SYNCCLREDGE_A::RISE)
136    }
137    #[doc = "Use falling edge detection"]
138    #[inline(always)]
139    pub fn fall(self) -> &'a mut W {
140        self.variant(SYNCCLREDGE_A::FALL)
141    }
142}
143impl R {
144    #[doc = "Bits 0:7 - Hardware Sync Trigger Set Edge Select"]
145    #[inline(always)]
146    pub fn syncsetedge(&self) -> SYNCSETEDGE_R {
147        SYNCSETEDGE_R::new((self.bits & 0xff) as u8)
148    }
149    #[doc = "Bits 16:23 - Hardware Sync Trigger Clear Edge Select"]
150    #[inline(always)]
151    pub fn syncclredge(&self) -> SYNCCLREDGE_R {
152        SYNCCLREDGE_R::new(((self.bits >> 16) & 0xff) as u8)
153    }
154}
155impl W {
156    #[doc = "Bits 0:7 - Hardware Sync Trigger Set Edge Select"]
157    #[inline(always)]
158    #[must_use]
159    pub fn syncsetedge(&mut self) -> SYNCSETEDGE_W<0> {
160        SYNCSETEDGE_W::new(self)
161    }
162    #[doc = "Bits 16:23 - Hardware Sync Trigger Clear Edge Select"]
163    #[inline(always)]
164    #[must_use]
165    pub fn syncclredge(&mut self) -> SYNCCLREDGE_W<16> {
166        SYNCCLREDGE_W::new(self)
167    }
168    #[doc = "Writes raw bits to the register."]
169    #[inline(always)]
170    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
171        self.0.bits(bits);
172        self
173    }
174}
175#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [synchwsel](index.html) module"]
176pub struct SYNCHWSEL_SPEC;
177impl crate::RegisterSpec for SYNCHWSEL_SPEC {
178    type Ux = u32;
179}
180#[doc = "`read()` method returns [synchwsel::R](R) reader structure"]
181impl crate::Readable for SYNCHWSEL_SPEC {
182    type Reader = R;
183}
184#[doc = "`write(|w| ..)` method takes [synchwsel::W](W) writer structure"]
185impl crate::Writable for SYNCHWSEL_SPEC {
186    type Writer = W;
187    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
188    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
189}
190#[doc = "`reset()` method sets SYNCHWSEL to value 0"]
191impl crate::Resettable for SYNCHWSEL_SPEC {
192    const RESET_VALUE: Self::Ux = 0;
193}
efm32pg22_pac/efm32pg22c200/ldma_s/synchwsel.rs

efm32pg22_pac/efm32pg22c200/ldma_s/
synchwsel.rs
