efm32pg22_pac/efm32pg22c200/icache0_s/
lpmode.rs

1#[doc = "Register `LPMODE` reader"]
2pub struct R(crate::R<LPMODE_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<LPMODE_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<LPMODE_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<LPMODE_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `LPMODE` writer"]
17pub struct W(crate::W<LPMODE_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<LPMODE_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<LPMODE_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<LPMODE_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `LPLEVEL` reader - Low Power Level"]
38pub type LPLEVEL_R = crate::FieldReader<u8, LPLEVEL_A>;
39#[doc = "Low Power Level\n\nValue on reset: 3"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum LPLEVEL_A {
43    #[doc = "0: Base instruction cache functionality"]
44    BASIC = 0,
45    #[doc = "1: Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory"]
46    ADVANCED = 1,
47    #[doc = "3: Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality."]
48    MINACTIVITY = 3,
49}
50impl From<LPLEVEL_A> for u8 {
51    #[inline(always)]
52    fn from(variant: LPLEVEL_A) -> Self {
53        variant as _
54    }
55}
56impl LPLEVEL_R {
57    #[doc = "Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> Option<LPLEVEL_A> {
60        match self.bits {
61            0 => Some(LPLEVEL_A::BASIC),
62            1 => Some(LPLEVEL_A::ADVANCED),
63            3 => Some(LPLEVEL_A::MINACTIVITY),
64            _ => None,
65        }
66    }
67    #[doc = "Checks if the value of the field is `BASIC`"]
68    #[inline(always)]
69    pub fn is_basic(&self) -> bool {
70        *self == LPLEVEL_A::BASIC
71    }
72    #[doc = "Checks if the value of the field is `ADVANCED`"]
73    #[inline(always)]
74    pub fn is_advanced(&self) -> bool {
75        *self == LPLEVEL_A::ADVANCED
76    }
77    #[doc = "Checks if the value of the field is `MINACTIVITY`"]
78    #[inline(always)]
79    pub fn is_minactivity(&self) -> bool {
80        *self == LPLEVEL_A::MINACTIVITY
81    }
82}
83#[doc = "Field `LPLEVEL` writer - Low Power Level"]
84pub type LPLEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LPMODE_SPEC, u8, LPLEVEL_A, 2, O>;
85impl<'a, const O: u8> LPLEVEL_W<'a, O> {
86    #[doc = "Base instruction cache functionality"]
87    #[inline(always)]
88    pub fn basic(self) -> &'a mut W {
89        self.variant(LPLEVEL_A::BASIC)
90    }
91    #[doc = "Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory"]
92    #[inline(always)]
93    pub fn advanced(self) -> &'a mut W {
94        self.variant(LPLEVEL_A::ADVANCED)
95    }
96    #[doc = "Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality."]
97    #[inline(always)]
98    pub fn minactivity(self) -> &'a mut W {
99        self.variant(LPLEVEL_A::MINACTIVITY)
100    }
101}
102#[doc = "Field `NESTFACTOR` reader - Low Power Nest Factor"]
103pub type NESTFACTOR_R = crate::FieldReader<u8, u8>;
104#[doc = "Field `NESTFACTOR` writer - Low Power Nest Factor"]
105pub type NESTFACTOR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LPMODE_SPEC, u8, u8, 4, O>;
106impl R {
107    #[doc = "Bits 0:1 - Low Power Level"]
108    #[inline(always)]
109    pub fn lplevel(&self) -> LPLEVEL_R {
110        LPLEVEL_R::new((self.bits & 3) as u8)
111    }
112    #[doc = "Bits 4:7 - Low Power Nest Factor"]
113    #[inline(always)]
114    pub fn nestfactor(&self) -> NESTFACTOR_R {
115        NESTFACTOR_R::new(((self.bits >> 4) & 0x0f) as u8)
116    }
117}
118impl W {
119    #[doc = "Bits 0:1 - Low Power Level"]
120    #[inline(always)]
121    #[must_use]
122    pub fn lplevel(&mut self) -> LPLEVEL_W<0> {
123        LPLEVEL_W::new(self)
124    }
125    #[doc = "Bits 4:7 - Low Power Nest Factor"]
126    #[inline(always)]
127    #[must_use]
128    pub fn nestfactor(&mut self) -> NESTFACTOR_W<4> {
129        NESTFACTOR_W::new(self)
130    }
131    #[doc = "Writes raw bits to the register."]
132    #[inline(always)]
133    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
134        self.0.bits(bits);
135        self
136    }
137}
138#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lpmode](index.html) module"]
139pub struct LPMODE_SPEC;
140impl crate::RegisterSpec for LPMODE_SPEC {
141    type Ux = u32;
142}
143#[doc = "`read()` method returns [lpmode::R](R) reader structure"]
144impl crate::Readable for LPMODE_SPEC {
145    type Reader = R;
146}
147#[doc = "`write(|w| ..)` method takes [lpmode::W](W) writer structure"]
148impl crate::Writable for LPMODE_SPEC {
149    type Writer = W;
150    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
151    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
152}
153#[doc = "`reset()` method sets LPMODE to value 0x23"]
154impl crate::Resettable for LPMODE_SPEC {
155    const RESET_VALUE: Self::Ux = 0x23;
156}
efm32pg22_pac/efm32pg22c200/icache0_s/lpmode.rs

efm32pg22_pac/efm32pg22c200/icache0_s/
lpmode.rs
