efm32pg22_pac/efm32pg22c200/iadc0_s/
status.rs

1#[doc = "Register `STATUS` reader"]
2pub struct R(crate::R<STATUS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<STATUS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<STATUS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<STATUS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `SINGLEQEN` reader - Single Queue Enabled"]
17pub type SINGLEQEN_R = crate::BitReader<bool>;
18#[doc = "Field `SINGLEQUEUEPENDING` reader - Single Queue Pending"]
19pub type SINGLEQUEUEPENDING_R = crate::BitReader<bool>;
20#[doc = "Field `SCANQEN` reader - Scan Queued Enabled"]
21pub type SCANQEN_R = crate::BitReader<bool>;
22#[doc = "Field `SCANQUEUEPENDING` reader - Scan Queue Pending"]
23pub type SCANQUEUEPENDING_R = crate::BitReader<bool>;
24#[doc = "Field `CONVERTING` reader - Converting"]
25pub type CONVERTING_R = crate::BitReader<bool>;
26#[doc = "Field `SINGLEFIFODV` reader - SINGLEFIFO Data Valid"]
27pub type SINGLEFIFODV_R = crate::BitReader<bool>;
28#[doc = "Field `SCANFIFODV` reader - SCANFIFO Data Valid"]
29pub type SCANFIFODV_R = crate::BitReader<bool>;
30#[doc = "Field `SINGLEFIFOFLUSHING` reader - The Single FIFO is flushing"]
31pub type SINGLEFIFOFLUSHING_R = crate::BitReader<bool>;
32#[doc = "Field `SCANFIFOFLUSHING` reader - The Scan FIFO is flushing"]
33pub type SCANFIFOFLUSHING_R = crate::BitReader<bool>;
34#[doc = "Field `TIMERACTIVE` reader - Timer Active"]
35pub type TIMERACTIVE_R = crate::BitReader<bool>;
36#[doc = "Field `SINGLEWRITEPENDING` reader - SINGLE write pending"]
37pub type SINGLEWRITEPENDING_R = crate::BitReader<bool>;
38#[doc = "Field `MASKREQWRITEPENDING` reader - MASKREQ write pending"]
39pub type MASKREQWRITEPENDING_R = crate::BitReader<bool>;
40#[doc = "Field `SYNCBUSY` reader - SYNCBUSY"]
41pub type SYNCBUSY_R = crate::BitReader<bool>;
42#[doc = "Field `ADCWARM` reader - ADCWARM"]
43pub type ADCWARM_R = crate::BitReader<bool>;
44impl R {
45    #[doc = "Bit 0 - Single Queue Enabled"]
46    #[inline(always)]
47    pub fn singleqen(&self) -> SINGLEQEN_R {
48        SINGLEQEN_R::new((self.bits & 1) != 0)
49    }
50    #[doc = "Bit 1 - Single Queue Pending"]
51    #[inline(always)]
52    pub fn singlequeuepending(&self) -> SINGLEQUEUEPENDING_R {
53        SINGLEQUEUEPENDING_R::new(((self.bits >> 1) & 1) != 0)
54    }
55    #[doc = "Bit 3 - Scan Queued Enabled"]
56    #[inline(always)]
57    pub fn scanqen(&self) -> SCANQEN_R {
58        SCANQEN_R::new(((self.bits >> 3) & 1) != 0)
59    }
60    #[doc = "Bit 4 - Scan Queue Pending"]
61    #[inline(always)]
62    pub fn scanqueuepending(&self) -> SCANQUEUEPENDING_R {
63        SCANQUEUEPENDING_R::new(((self.bits >> 4) & 1) != 0)
64    }
65    #[doc = "Bit 6 - Converting"]
66    #[inline(always)]
67    pub fn converting(&self) -> CONVERTING_R {
68        CONVERTING_R::new(((self.bits >> 6) & 1) != 0)
69    }
70    #[doc = "Bit 8 - SINGLEFIFO Data Valid"]
71    #[inline(always)]
72    pub fn singlefifodv(&self) -> SINGLEFIFODV_R {
73        SINGLEFIFODV_R::new(((self.bits >> 8) & 1) != 0)
74    }
75    #[doc = "Bit 9 - SCANFIFO Data Valid"]
76    #[inline(always)]
77    pub fn scanfifodv(&self) -> SCANFIFODV_R {
78        SCANFIFODV_R::new(((self.bits >> 9) & 1) != 0)
79    }
80    #[doc = "Bit 14 - The Single FIFO is flushing"]
81    #[inline(always)]
82    pub fn singlefifoflushing(&self) -> SINGLEFIFOFLUSHING_R {
83        SINGLEFIFOFLUSHING_R::new(((self.bits >> 14) & 1) != 0)
84    }
85    #[doc = "Bit 15 - The Scan FIFO is flushing"]
86    #[inline(always)]
87    pub fn scanfifoflushing(&self) -> SCANFIFOFLUSHING_R {
88        SCANFIFOFLUSHING_R::new(((self.bits >> 15) & 1) != 0)
89    }
90    #[doc = "Bit 16 - Timer Active"]
91    #[inline(always)]
92    pub fn timeractive(&self) -> TIMERACTIVE_R {
93        TIMERACTIVE_R::new(((self.bits >> 16) & 1) != 0)
94    }
95    #[doc = "Bit 20 - SINGLE write pending"]
96    #[inline(always)]
97    pub fn singlewritepending(&self) -> SINGLEWRITEPENDING_R {
98        SINGLEWRITEPENDING_R::new(((self.bits >> 20) & 1) != 0)
99    }
100    #[doc = "Bit 21 - MASKREQ write pending"]
101    #[inline(always)]
102    pub fn maskreqwritepending(&self) -> MASKREQWRITEPENDING_R {
103        MASKREQWRITEPENDING_R::new(((self.bits >> 21) & 1) != 0)
104    }
105    #[doc = "Bit 24 - SYNCBUSY"]
106    #[inline(always)]
107    pub fn syncbusy(&self) -> SYNCBUSY_R {
108        SYNCBUSY_R::new(((self.bits >> 24) & 1) != 0)
109    }
110    #[doc = "Bit 30 - ADCWARM"]
111    #[inline(always)]
112    pub fn adcwarm(&self) -> ADCWARM_R {
113        ADCWARM_R::new(((self.bits >> 30) & 1) != 0)
114    }
115}
116#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
117pub struct STATUS_SPEC;
118impl crate::RegisterSpec for STATUS_SPEC {
119    type Ux = u32;
120}
121#[doc = "`read()` method returns [status::R](R) reader structure"]
122impl crate::Readable for STATUS_SPEC {
123    type Reader = R;
124}
125#[doc = "`reset()` method sets STATUS to value 0"]
126impl crate::Resettable for STATUS_SPEC {
127    const RESET_VALUE: Self::Ux = 0;
128}
efm32pg22_pac/efm32pg22c200/iadc0_s/status.rs

efm32pg22_pac/efm32pg22c200/iadc0_s/
status.rs
