efm32pg22_pac/efm32pg22c200/iadc0_ns/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `EM23WUCONVERT` reader - EM23 Wakeup on Conversion"]
38pub type EM23WUCONVERT_R = crate::BitReader<EM23WUCONVERT_A>;
39#[doc = "EM23 Wakeup on Conversion\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum EM23WUCONVERT_A {
42    #[doc = "0: When using suspend mode, conversions performed in EM2 or EM3 should not wake up the DMA until the FIFO's DVL setting is reached. This saves more power for large OSR settings or infrequent sampling."]
43    WUDVL = 0,
44    #[doc = "1: When using suspend mode, conversions performed in EM2 or EM3 will wake up the DMA and keep it awake until the conversions are done, regardless of the DVL setting. This mode burns more power, but it is useful when the conversion rate is faster than the time for the DMA to cycle through wake up and going back to sleep as it converts more than 4 scan table entries. Without using the wake up on conversion mode, the FIFO may overflow while the DMA is going in and out of sleep."]
45    WUCONVERT = 1,
46}
47impl From<EM23WUCONVERT_A> for bool {
48    #[inline(always)]
49    fn from(variant: EM23WUCONVERT_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl EM23WUCONVERT_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> EM23WUCONVERT_A {
57        match self.bits {
58            false => EM23WUCONVERT_A::WUDVL,
59            true => EM23WUCONVERT_A::WUCONVERT,
60        }
61    }
62    #[doc = "Checks if the value of the field is `WUDVL`"]
63    #[inline(always)]
64    pub fn is_wudvl(&self) -> bool {
65        *self == EM23WUCONVERT_A::WUDVL
66    }
67    #[doc = "Checks if the value of the field is `WUCONVERT`"]
68    #[inline(always)]
69    pub fn is_wuconvert(&self) -> bool {
70        *self == EM23WUCONVERT_A::WUCONVERT
71    }
72}
73#[doc = "Field `EM23WUCONVERT` writer - EM23 Wakeup on Conversion"]
74pub type EM23WUCONVERT_W<'a, const O: u8> =
75    crate::BitWriter<'a, u32, CTRL_SPEC, EM23WUCONVERT_A, O>;
76impl<'a, const O: u8> EM23WUCONVERT_W<'a, O> {
77    #[doc = "When using suspend mode, conversions performed in EM2 or EM3 should not wake up the DMA until the FIFO's DVL setting is reached. This saves more power for large OSR settings or infrequent sampling."]
78    #[inline(always)]
79    pub fn wudvl(self) -> &'a mut W {
80        self.variant(EM23WUCONVERT_A::WUDVL)
81    }
82    #[doc = "When using suspend mode, conversions performed in EM2 or EM3 will wake up the DMA and keep it awake until the conversions are done, regardless of the DVL setting. This mode burns more power, but it is useful when the conversion rate is faster than the time for the DMA to cycle through wake up and going back to sleep as it converts more than 4 scan table entries. Without using the wake up on conversion mode, the FIFO may overflow while the DMA is going in and out of sleep."]
83    #[inline(always)]
84    pub fn wuconvert(self) -> &'a mut W {
85        self.variant(EM23WUCONVERT_A::WUCONVERT)
86    }
87}
88#[doc = "Field `ADCCLKSUSPEND0` reader - ADC_CLK Suspend - PRS0"]
89pub type ADCCLKSUSPEND0_R = crate::BitReader<ADCCLKSUSPEND0_A>;
90#[doc = "ADC_CLK Suspend - PRS0\n\nValue on reset: 0"]
91#[derive(Clone, Copy, Debug, PartialEq, Eq)]
92pub enum ADCCLKSUSPEND0_A {
93    #[doc = "0: Normal mode which does not disable the ADC_CLK."]
94    PRSWUDIS = 0,
95    #[doc = "1: ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off."]
96    PRSWUEN = 1,
97}
98impl From<ADCCLKSUSPEND0_A> for bool {
99    #[inline(always)]
100    fn from(variant: ADCCLKSUSPEND0_A) -> Self {
101        variant as u8 != 0
102    }
103}
104impl ADCCLKSUSPEND0_R {
105    #[doc = "Get enumerated values variant"]
106    #[inline(always)]
107    pub fn variant(&self) -> ADCCLKSUSPEND0_A {
108        match self.bits {
109            false => ADCCLKSUSPEND0_A::PRSWUDIS,
110            true => ADCCLKSUSPEND0_A::PRSWUEN,
111        }
112    }
113    #[doc = "Checks if the value of the field is `PRSWUDIS`"]
114    #[inline(always)]
115    pub fn is_prswudis(&self) -> bool {
116        *self == ADCCLKSUSPEND0_A::PRSWUDIS
117    }
118    #[doc = "Checks if the value of the field is `PRSWUEN`"]
119    #[inline(always)]
120    pub fn is_prswuen(&self) -> bool {
121        *self == ADCCLKSUSPEND0_A::PRSWUEN
122    }
123}
124#[doc = "Field `ADCCLKSUSPEND0` writer - ADC_CLK Suspend - PRS0"]
125pub type ADCCLKSUSPEND0_W<'a, const O: u8> =
126    crate::BitWriter<'a, u32, CTRL_SPEC, ADCCLKSUSPEND0_A, O>;
127impl<'a, const O: u8> ADCCLKSUSPEND0_W<'a, O> {
128    #[doc = "Normal mode which does not disable the ADC_CLK."]
129    #[inline(always)]
130    pub fn prswudis(self) -> &'a mut W {
131        self.variant(ADCCLKSUSPEND0_A::PRSWUDIS)
132    }
133    #[doc = "ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off."]
134    #[inline(always)]
135    pub fn prswuen(self) -> &'a mut W {
136        self.variant(ADCCLKSUSPEND0_A::PRSWUEN)
137    }
138}
139#[doc = "Field `ADCCLKSUSPEND1` reader - ADC_CLK Suspend - PRS1"]
140pub type ADCCLKSUSPEND1_R = crate::BitReader<ADCCLKSUSPEND1_A>;
141#[doc = "ADC_CLK Suspend - PRS1\n\nValue on reset: 0"]
142#[derive(Clone, Copy, Debug, PartialEq, Eq)]
143pub enum ADCCLKSUSPEND1_A {
144    #[doc = "0: Normal mode which does not disable the ADC_CLK."]
145    PRSWUDIS = 0,
146    #[doc = "1: ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off."]
147    PRSWUEN = 1,
148}
149impl From<ADCCLKSUSPEND1_A> for bool {
150    #[inline(always)]
151    fn from(variant: ADCCLKSUSPEND1_A) -> Self {
152        variant as u8 != 0
153    }
154}
155impl ADCCLKSUSPEND1_R {
156    #[doc = "Get enumerated values variant"]
157    #[inline(always)]
158    pub fn variant(&self) -> ADCCLKSUSPEND1_A {
159        match self.bits {
160            false => ADCCLKSUSPEND1_A::PRSWUDIS,
161            true => ADCCLKSUSPEND1_A::PRSWUEN,
162        }
163    }
164    #[doc = "Checks if the value of the field is `PRSWUDIS`"]
165    #[inline(always)]
166    pub fn is_prswudis(&self) -> bool {
167        *self == ADCCLKSUSPEND1_A::PRSWUDIS
168    }
169    #[doc = "Checks if the value of the field is `PRSWUEN`"]
170    #[inline(always)]
171    pub fn is_prswuen(&self) -> bool {
172        *self == ADCCLKSUSPEND1_A::PRSWUEN
173    }
174}
175#[doc = "Field `ADCCLKSUSPEND1` writer - ADC_CLK Suspend - PRS1"]
176pub type ADCCLKSUSPEND1_W<'a, const O: u8> =
177    crate::BitWriter<'a, u32, CTRL_SPEC, ADCCLKSUSPEND1_A, O>;
178impl<'a, const O: u8> ADCCLKSUSPEND1_W<'a, O> {
179    #[doc = "Normal mode which does not disable the ADC_CLK."]
180    #[inline(always)]
181    pub fn prswudis(self) -> &'a mut W {
182        self.variant(ADCCLKSUSPEND1_A::PRSWUDIS)
183    }
184    #[doc = "ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off."]
185    #[inline(always)]
186    pub fn prswuen(self) -> &'a mut W {
187        self.variant(ADCCLKSUSPEND1_A::PRSWUEN)
188    }
189}
190#[doc = "Field `DBGHALT` reader - Debug Halt"]
191pub type DBGHALT_R = crate::BitReader<DBGHALT_A>;
192#[doc = "Debug Halt\n\nValue on reset: 0"]
193#[derive(Clone, Copy, Debug, PartialEq, Eq)]
194pub enum DBGHALT_A {
195    #[doc = "0: Continue operation as normal during debug mode"]
196    NORMAL = 0,
197    #[doc = "1: Complete the current conversion and then halt during debug mode"]
198    HALT = 1,
199}
200impl From<DBGHALT_A> for bool {
201    #[inline(always)]
202    fn from(variant: DBGHALT_A) -> Self {
203        variant as u8 != 0
204    }
205}
206impl DBGHALT_R {
207    #[doc = "Get enumerated values variant"]
208    #[inline(always)]
209    pub fn variant(&self) -> DBGHALT_A {
210        match self.bits {
211            false => DBGHALT_A::NORMAL,
212            true => DBGHALT_A::HALT,
213        }
214    }
215    #[doc = "Checks if the value of the field is `NORMAL`"]
216    #[inline(always)]
217    pub fn is_normal(&self) -> bool {
218        *self == DBGHALT_A::NORMAL
219    }
220    #[doc = "Checks if the value of the field is `HALT`"]
221    #[inline(always)]
222    pub fn is_halt(&self) -> bool {
223        *self == DBGHALT_A::HALT
224    }
225}
226#[doc = "Field `DBGHALT` writer - Debug Halt"]
227pub type DBGHALT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, DBGHALT_A, O>;
228impl<'a, const O: u8> DBGHALT_W<'a, O> {
229    #[doc = "Continue operation as normal during debug mode"]
230    #[inline(always)]
231    pub fn normal(self) -> &'a mut W {
232        self.variant(DBGHALT_A::NORMAL)
233    }
234    #[doc = "Complete the current conversion and then halt during debug mode"]
235    #[inline(always)]
236    pub fn halt(self) -> &'a mut W {
237        self.variant(DBGHALT_A::HALT)
238    }
239}
240#[doc = "Field `WARMUPMODE` reader - Warmup Mode"]
241pub type WARMUPMODE_R = crate::FieldReader<u8, WARMUPMODE_A>;
242#[doc = "Warmup Mode\n\nValue on reset: 0"]
243#[derive(Clone, Copy, Debug, PartialEq, Eq)]
244#[repr(u8)]
245pub enum WARMUPMODE_A {
246    #[doc = "0: Shut down the IADC after conversions have completed."]
247    NORMAL = 0,
248    #[doc = "1: Switch to standby mode after conversions have completed. The next warmup time will require 1us."]
249    KEEPINSTANDBY = 1,
250    #[doc = "2: Keep IADC fully powered after conversions have completed."]
251    KEEPWARM = 2,
252}
253impl From<WARMUPMODE_A> for u8 {
254    #[inline(always)]
255    fn from(variant: WARMUPMODE_A) -> Self {
256        variant as _
257    }
258}
259impl WARMUPMODE_R {
260    #[doc = "Get enumerated values variant"]
261    #[inline(always)]
262    pub fn variant(&self) -> Option<WARMUPMODE_A> {
263        match self.bits {
264            0 => Some(WARMUPMODE_A::NORMAL),
265            1 => Some(WARMUPMODE_A::KEEPINSTANDBY),
266            2 => Some(WARMUPMODE_A::KEEPWARM),
267            _ => None,
268        }
269    }
270    #[doc = "Checks if the value of the field is `NORMAL`"]
271    #[inline(always)]
272    pub fn is_normal(&self) -> bool {
273        *self == WARMUPMODE_A::NORMAL
274    }
275    #[doc = "Checks if the value of the field is `KEEPINSTANDBY`"]
276    #[inline(always)]
277    pub fn is_keepinstandby(&self) -> bool {
278        *self == WARMUPMODE_A::KEEPINSTANDBY
279    }
280    #[doc = "Checks if the value of the field is `KEEPWARM`"]
281    #[inline(always)]
282    pub fn is_keepwarm(&self) -> bool {
283        *self == WARMUPMODE_A::KEEPWARM
284    }
285}
286#[doc = "Field `WARMUPMODE` writer - Warmup Mode"]
287pub type WARMUPMODE_W<'a, const O: u8> =
288    crate::FieldWriter<'a, u32, CTRL_SPEC, u8, WARMUPMODE_A, 2, O>;
289impl<'a, const O: u8> WARMUPMODE_W<'a, O> {
290    #[doc = "Shut down the IADC after conversions have completed."]
291    #[inline(always)]
292    pub fn normal(self) -> &'a mut W {
293        self.variant(WARMUPMODE_A::NORMAL)
294    }
295    #[doc = "Switch to standby mode after conversions have completed. The next warmup time will require 1us."]
296    #[inline(always)]
297    pub fn keepinstandby(self) -> &'a mut W {
298        self.variant(WARMUPMODE_A::KEEPINSTANDBY)
299    }
300    #[doc = "Keep IADC fully powered after conversions have completed."]
301    #[inline(always)]
302    pub fn keepwarm(self) -> &'a mut W {
303        self.variant(WARMUPMODE_A::KEEPWARM)
304    }
305}
306#[doc = "Field `TIMEBASE` reader - Time Base"]
307pub type TIMEBASE_R = crate::FieldReader<u8, u8>;
308#[doc = "Field `TIMEBASE` writer - Time Base"]
309pub type TIMEBASE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 7, O>;
310#[doc = "Field `HSCLKRATE` reader - High Speed Clock Rate"]
311pub type HSCLKRATE_R = crate::FieldReader<u8, HSCLKRATE_A>;
312#[doc = "High Speed Clock Rate\n\nValue on reset: 0"]
313#[derive(Clone, Copy, Debug, PartialEq, Eq)]
314#[repr(u8)]
315pub enum HSCLKRATE_A {
316    #[doc = "0: Use CMU_CLK_ADC directly. The source clock must be 40 MHz or less."]
317    DIV1 = 0,
318    #[doc = "1: Divide CMU_CLK_ADC by 2 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less."]
319    DIV2 = 1,
320    #[doc = "2: Divide CMU_CLK_ADC by 3 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less."]
321    DIV3 = 2,
322    #[doc = "3: Divide CMU_CLK_ADC by 4 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less."]
323    DIV4 = 3,
324}
325impl From<HSCLKRATE_A> for u8 {
326    #[inline(always)]
327    fn from(variant: HSCLKRATE_A) -> Self {
328        variant as _
329    }
330}
331impl HSCLKRATE_R {
332    #[doc = "Get enumerated values variant"]
333    #[inline(always)]
334    pub fn variant(&self) -> Option<HSCLKRATE_A> {
335        match self.bits {
336            0 => Some(HSCLKRATE_A::DIV1),
337            1 => Some(HSCLKRATE_A::DIV2),
338            2 => Some(HSCLKRATE_A::DIV3),
339            3 => Some(HSCLKRATE_A::DIV4),
340            _ => None,
341        }
342    }
343    #[doc = "Checks if the value of the field is `DIV1`"]
344    #[inline(always)]
345    pub fn is_div1(&self) -> bool {
346        *self == HSCLKRATE_A::DIV1
347    }
348    #[doc = "Checks if the value of the field is `DIV2`"]
349    #[inline(always)]
350    pub fn is_div2(&self) -> bool {
351        *self == HSCLKRATE_A::DIV2
352    }
353    #[doc = "Checks if the value of the field is `DIV3`"]
354    #[inline(always)]
355    pub fn is_div3(&self) -> bool {
356        *self == HSCLKRATE_A::DIV3
357    }
358    #[doc = "Checks if the value of the field is `DIV4`"]
359    #[inline(always)]
360    pub fn is_div4(&self) -> bool {
361        *self == HSCLKRATE_A::DIV4
362    }
363}
364#[doc = "Field `HSCLKRATE` writer - High Speed Clock Rate"]
365pub type HSCLKRATE_W<'a, const O: u8> =
366    crate::FieldWriter<'a, u32, CTRL_SPEC, u8, HSCLKRATE_A, 3, O>;
367impl<'a, const O: u8> HSCLKRATE_W<'a, O> {
368    #[doc = "Use CMU_CLK_ADC directly. The source clock must be 40 MHz or less."]
369    #[inline(always)]
370    pub fn div1(self) -> &'a mut W {
371        self.variant(HSCLKRATE_A::DIV1)
372    }
373    #[doc = "Divide CMU_CLK_ADC by 2 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less."]
374    #[inline(always)]
375    pub fn div2(self) -> &'a mut W {
376        self.variant(HSCLKRATE_A::DIV2)
377    }
378    #[doc = "Divide CMU_CLK_ADC by 3 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less."]
379    #[inline(always)]
380    pub fn div3(self) -> &'a mut W {
381        self.variant(HSCLKRATE_A::DIV3)
382    }
383    #[doc = "Divide CMU_CLK_ADC by 4 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less."]
384    #[inline(always)]
385    pub fn div4(self) -> &'a mut W {
386        self.variant(HSCLKRATE_A::DIV4)
387    }
388}
389impl R {
390    #[doc = "Bit 0 - EM23 Wakeup on Conversion"]
391    #[inline(always)]
392    pub fn em23wuconvert(&self) -> EM23WUCONVERT_R {
393        EM23WUCONVERT_R::new((self.bits & 1) != 0)
394    }
395    #[doc = "Bit 1 - ADC_CLK Suspend - PRS0"]
396    #[inline(always)]
397    pub fn adcclksuspend0(&self) -> ADCCLKSUSPEND0_R {
398        ADCCLKSUSPEND0_R::new(((self.bits >> 1) & 1) != 0)
399    }
400    #[doc = "Bit 2 - ADC_CLK Suspend - PRS1"]
401    #[inline(always)]
402    pub fn adcclksuspend1(&self) -> ADCCLKSUSPEND1_R {
403        ADCCLKSUSPEND1_R::new(((self.bits >> 2) & 1) != 0)
404    }
405    #[doc = "Bit 3 - Debug Halt"]
406    #[inline(always)]
407    pub fn dbghalt(&self) -> DBGHALT_R {
408        DBGHALT_R::new(((self.bits >> 3) & 1) != 0)
409    }
410    #[doc = "Bits 4:5 - Warmup Mode"]
411    #[inline(always)]
412    pub fn warmupmode(&self) -> WARMUPMODE_R {
413        WARMUPMODE_R::new(((self.bits >> 4) & 3) as u8)
414    }
415    #[doc = "Bits 16:22 - Time Base"]
416    #[inline(always)]
417    pub fn timebase(&self) -> TIMEBASE_R {
418        TIMEBASE_R::new(((self.bits >> 16) & 0x7f) as u8)
419    }
420    #[doc = "Bits 28:30 - High Speed Clock Rate"]
421    #[inline(always)]
422    pub fn hsclkrate(&self) -> HSCLKRATE_R {
423        HSCLKRATE_R::new(((self.bits >> 28) & 7) as u8)
424    }
425}
426impl W {
427    #[doc = "Bit 0 - EM23 Wakeup on Conversion"]
428    #[inline(always)]
429    #[must_use]
430    pub fn em23wuconvert(&mut self) -> EM23WUCONVERT_W<0> {
431        EM23WUCONVERT_W::new(self)
432    }
433    #[doc = "Bit 1 - ADC_CLK Suspend - PRS0"]
434    #[inline(always)]
435    #[must_use]
436    pub fn adcclksuspend0(&mut self) -> ADCCLKSUSPEND0_W<1> {
437        ADCCLKSUSPEND0_W::new(self)
438    }
439    #[doc = "Bit 2 - ADC_CLK Suspend - PRS1"]
440    #[inline(always)]
441    #[must_use]
442    pub fn adcclksuspend1(&mut self) -> ADCCLKSUSPEND1_W<2> {
443        ADCCLKSUSPEND1_W::new(self)
444    }
445    #[doc = "Bit 3 - Debug Halt"]
446    #[inline(always)]
447    #[must_use]
448    pub fn dbghalt(&mut self) -> DBGHALT_W<3> {
449        DBGHALT_W::new(self)
450    }
451    #[doc = "Bits 4:5 - Warmup Mode"]
452    #[inline(always)]
453    #[must_use]
454    pub fn warmupmode(&mut self) -> WARMUPMODE_W<4> {
455        WARMUPMODE_W::new(self)
456    }
457    #[doc = "Bits 16:22 - Time Base"]
458    #[inline(always)]
459    #[must_use]
460    pub fn timebase(&mut self) -> TIMEBASE_W<16> {
461        TIMEBASE_W::new(self)
462    }
463    #[doc = "Bits 28:30 - High Speed Clock Rate"]
464    #[inline(always)]
465    #[must_use]
466    pub fn hsclkrate(&mut self) -> HSCLKRATE_W<28> {
467        HSCLKRATE_W::new(self)
468    }
469    #[doc = "Writes raw bits to the register."]
470    #[inline(always)]
471    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
472        self.0.bits(bits);
473        self
474    }
475}
476#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
477pub struct CTRL_SPEC;
478impl crate::RegisterSpec for CTRL_SPEC {
479    type Ux = u32;
480}
481#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
482impl crate::Readable for CTRL_SPEC {
483    type Reader = R;
484}
485#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
486impl crate::Writable for CTRL_SPEC {
487    type Writer = W;
488    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
489    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
490}
491#[doc = "`reset()` method sets CTRL to value 0"]
492impl crate::Resettable for CTRL_SPEC {
493    const RESET_VALUE: Self::Ux = 0;
494}
efm32pg22_pac/efm32pg22c200/iadc0_ns/ctrl.rs

efm32pg22_pac/efm32pg22c200/iadc0_ns/
ctrl.rs
