efm32pg22_pac/efm32pg22c200/gpio_s/
timer3_cdti0route.rs

1#[doc = "Register `TIMER3_CDTI0ROUTE` reader"]
2pub struct R(crate::R<TIMER3_CDTI0ROUTE_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<TIMER3_CDTI0ROUTE_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<TIMER3_CDTI0ROUTE_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<TIMER3_CDTI0ROUTE_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `TIMER3_CDTI0ROUTE` writer"]
17pub struct W(crate::W<TIMER3_CDTI0ROUTE_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<TIMER3_CDTI0ROUTE_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<TIMER3_CDTI0ROUTE_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<TIMER3_CDTI0ROUTE_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PORT` reader - CDTI0 port select register"]
38pub type PORT_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `PORT` writer - CDTI0 port select register"]
40pub type PORT_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, TIMER3_CDTI0ROUTE_SPEC, u8, u8, 2, O>;
42#[doc = "Field `PIN` reader - CDTI0 pin select register"]
43pub type PIN_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `PIN` writer - CDTI0 pin select register"]
45pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TIMER3_CDTI0ROUTE_SPEC, u8, u8, 4, O>;
46impl R {
47    #[doc = "Bits 0:1 - CDTI0 port select register"]
48    #[inline(always)]
49    pub fn port(&self) -> PORT_R {
50        PORT_R::new((self.bits & 3) as u8)
51    }
52    #[doc = "Bits 16:19 - CDTI0 pin select register"]
53    #[inline(always)]
54    pub fn pin(&self) -> PIN_R {
55        PIN_R::new(((self.bits >> 16) & 0x0f) as u8)
56    }
57}
58impl W {
59    #[doc = "Bits 0:1 - CDTI0 port select register"]
60    #[inline(always)]
61    #[must_use]
62    pub fn port(&mut self) -> PORT_W<0> {
63        PORT_W::new(self)
64    }
65    #[doc = "Bits 16:19 - CDTI0 pin select register"]
66    #[inline(always)]
67    #[must_use]
68    pub fn pin(&mut self) -> PIN_W<16> {
69        PIN_W::new(self)
70    }
71    #[doc = "Writes raw bits to the register."]
72    #[inline(always)]
73    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
74        self.0.bits(bits);
75        self
76    }
77}
78#[doc = "CDTI0 port/pin select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timer3_cdti0route](index.html) module"]
79pub struct TIMER3_CDTI0ROUTE_SPEC;
80impl crate::RegisterSpec for TIMER3_CDTI0ROUTE_SPEC {
81    type Ux = u32;
82}
83#[doc = "`read()` method returns [timer3_cdti0route::R](R) reader structure"]
84impl crate::Readable for TIMER3_CDTI0ROUTE_SPEC {
85    type Reader = R;
86}
87#[doc = "`write(|w| ..)` method takes [timer3_cdti0route::W](W) writer structure"]
88impl crate::Writable for TIMER3_CDTI0ROUTE_SPEC {
89    type Writer = W;
90    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
91    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
92}
93#[doc = "`reset()` method sets TIMER3_CDTI0ROUTE to value 0"]
94impl crate::Resettable for TIMER3_CDTI0ROUTE_SPEC {
95    const RESET_VALUE: Self::Ux = 0;
96}
efm32pg22_pac/efm32pg22c200/gpio_s/timer3_cdti0route.rs

efm32pg22_pac/efm32pg22c200/gpio_s/
timer3_cdti0route.rs
