efm32pg22_pac/efm32pg22c200/gpio_s/
prs0_routeen.rs

1#[doc = "Register `PRS0_ROUTEEN` reader"]
2pub struct R(crate::R<PRS0_ROUTEEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PRS0_ROUTEEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PRS0_ROUTEEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PRS0_ROUTEEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PRS0_ROUTEEN` writer"]
17pub struct W(crate::W<PRS0_ROUTEEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PRS0_ROUTEEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PRS0_ROUTEEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PRS0_ROUTEEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ASYNCH0PEN` reader - ASYNCH0 pin enable control bit"]
38pub type ASYNCH0PEN_R = crate::BitReader<bool>;
39#[doc = "Field `ASYNCH0PEN` writer - ASYNCH0 pin enable control bit"]
40pub type ASYNCH0PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
41#[doc = "Field `ASYNCH1PEN` reader - ASYNCH1 pin enable control bit"]
42pub type ASYNCH1PEN_R = crate::BitReader<bool>;
43#[doc = "Field `ASYNCH1PEN` writer - ASYNCH1 pin enable control bit"]
44pub type ASYNCH1PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
45#[doc = "Field `ASYNCH2PEN` reader - ASYNCH2 pin enable control bit"]
46pub type ASYNCH2PEN_R = crate::BitReader<bool>;
47#[doc = "Field `ASYNCH2PEN` writer - ASYNCH2 pin enable control bit"]
48pub type ASYNCH2PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
49#[doc = "Field `ASYNCH3PEN` reader - ASYNCH3 pin enable control bit"]
50pub type ASYNCH3PEN_R = crate::BitReader<bool>;
51#[doc = "Field `ASYNCH3PEN` writer - ASYNCH3 pin enable control bit"]
52pub type ASYNCH3PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
53#[doc = "Field `ASYNCH4PEN` reader - ASYNCH4 pin enable control bit"]
54pub type ASYNCH4PEN_R = crate::BitReader<bool>;
55#[doc = "Field `ASYNCH4PEN` writer - ASYNCH4 pin enable control bit"]
56pub type ASYNCH4PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
57#[doc = "Field `ASYNCH5PEN` reader - ASYNCH5 pin enable control bit"]
58pub type ASYNCH5PEN_R = crate::BitReader<bool>;
59#[doc = "Field `ASYNCH5PEN` writer - ASYNCH5 pin enable control bit"]
60pub type ASYNCH5PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
61#[doc = "Field `ASYNCH6PEN` reader - ASYNCH6 pin enable control bit"]
62pub type ASYNCH6PEN_R = crate::BitReader<bool>;
63#[doc = "Field `ASYNCH6PEN` writer - ASYNCH6 pin enable control bit"]
64pub type ASYNCH6PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
65#[doc = "Field `ASYNCH7PEN` reader - ASYNCH7 pin enable control bit"]
66pub type ASYNCH7PEN_R = crate::BitReader<bool>;
67#[doc = "Field `ASYNCH7PEN` writer - ASYNCH7 pin enable control bit"]
68pub type ASYNCH7PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
69#[doc = "Field `ASYNCH8PEN` reader - ASYNCH8 pin enable control bit"]
70pub type ASYNCH8PEN_R = crate::BitReader<bool>;
71#[doc = "Field `ASYNCH8PEN` writer - ASYNCH8 pin enable control bit"]
72pub type ASYNCH8PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
73#[doc = "Field `ASYNCH9PEN` reader - ASYNCH9 pin enable control bit"]
74pub type ASYNCH9PEN_R = crate::BitReader<bool>;
75#[doc = "Field `ASYNCH9PEN` writer - ASYNCH9 pin enable control bit"]
76pub type ASYNCH9PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
77#[doc = "Field `ASYNCH10PEN` reader - ASYNCH10 pin enable control bit"]
78pub type ASYNCH10PEN_R = crate::BitReader<bool>;
79#[doc = "Field `ASYNCH10PEN` writer - ASYNCH10 pin enable control bit"]
80pub type ASYNCH10PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
81#[doc = "Field `ASYNCH11PEN` reader - ASYNCH11 pin enable control bit"]
82pub type ASYNCH11PEN_R = crate::BitReader<bool>;
83#[doc = "Field `ASYNCH11PEN` writer - ASYNCH11 pin enable control bit"]
84pub type ASYNCH11PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
85#[doc = "Field `SYNCH0PEN` reader - SYNCH0 pin enable control bit"]
86pub type SYNCH0PEN_R = crate::BitReader<bool>;
87#[doc = "Field `SYNCH0PEN` writer - SYNCH0 pin enable control bit"]
88pub type SYNCH0PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
89#[doc = "Field `SYNCH1PEN` reader - SYNCH1 pin enable control bit"]
90pub type SYNCH1PEN_R = crate::BitReader<bool>;
91#[doc = "Field `SYNCH1PEN` writer - SYNCH1 pin enable control bit"]
92pub type SYNCH1PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
93#[doc = "Field `SYNCH2PEN` reader - SYNCH2 pin enable control bit"]
94pub type SYNCH2PEN_R = crate::BitReader<bool>;
95#[doc = "Field `SYNCH2PEN` writer - SYNCH2 pin enable control bit"]
96pub type SYNCH2PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
97#[doc = "Field `SYNCH3PEN` reader - SYNCH3 pin enable control bit"]
98pub type SYNCH3PEN_R = crate::BitReader<bool>;
99#[doc = "Field `SYNCH3PEN` writer - SYNCH3 pin enable control bit"]
100pub type SYNCH3PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRS0_ROUTEEN_SPEC, bool, O>;
101impl R {
102    #[doc = "Bit 0 - ASYNCH0 pin enable control bit"]
103    #[inline(always)]
104    pub fn asynch0pen(&self) -> ASYNCH0PEN_R {
105        ASYNCH0PEN_R::new((self.bits & 1) != 0)
106    }
107    #[doc = "Bit 1 - ASYNCH1 pin enable control bit"]
108    #[inline(always)]
109    pub fn asynch1pen(&self) -> ASYNCH1PEN_R {
110        ASYNCH1PEN_R::new(((self.bits >> 1) & 1) != 0)
111    }
112    #[doc = "Bit 2 - ASYNCH2 pin enable control bit"]
113    #[inline(always)]
114    pub fn asynch2pen(&self) -> ASYNCH2PEN_R {
115        ASYNCH2PEN_R::new(((self.bits >> 2) & 1) != 0)
116    }
117    #[doc = "Bit 3 - ASYNCH3 pin enable control bit"]
118    #[inline(always)]
119    pub fn asynch3pen(&self) -> ASYNCH3PEN_R {
120        ASYNCH3PEN_R::new(((self.bits >> 3) & 1) != 0)
121    }
122    #[doc = "Bit 4 - ASYNCH4 pin enable control bit"]
123    #[inline(always)]
124    pub fn asynch4pen(&self) -> ASYNCH4PEN_R {
125        ASYNCH4PEN_R::new(((self.bits >> 4) & 1) != 0)
126    }
127    #[doc = "Bit 5 - ASYNCH5 pin enable control bit"]
128    #[inline(always)]
129    pub fn asynch5pen(&self) -> ASYNCH5PEN_R {
130        ASYNCH5PEN_R::new(((self.bits >> 5) & 1) != 0)
131    }
132    #[doc = "Bit 6 - ASYNCH6 pin enable control bit"]
133    #[inline(always)]
134    pub fn asynch6pen(&self) -> ASYNCH6PEN_R {
135        ASYNCH6PEN_R::new(((self.bits >> 6) & 1) != 0)
136    }
137    #[doc = "Bit 7 - ASYNCH7 pin enable control bit"]
138    #[inline(always)]
139    pub fn asynch7pen(&self) -> ASYNCH7PEN_R {
140        ASYNCH7PEN_R::new(((self.bits >> 7) & 1) != 0)
141    }
142    #[doc = "Bit 8 - ASYNCH8 pin enable control bit"]
143    #[inline(always)]
144    pub fn asynch8pen(&self) -> ASYNCH8PEN_R {
145        ASYNCH8PEN_R::new(((self.bits >> 8) & 1) != 0)
146    }
147    #[doc = "Bit 9 - ASYNCH9 pin enable control bit"]
148    #[inline(always)]
149    pub fn asynch9pen(&self) -> ASYNCH9PEN_R {
150        ASYNCH9PEN_R::new(((self.bits >> 9) & 1) != 0)
151    }
152    #[doc = "Bit 10 - ASYNCH10 pin enable control bit"]
153    #[inline(always)]
154    pub fn asynch10pen(&self) -> ASYNCH10PEN_R {
155        ASYNCH10PEN_R::new(((self.bits >> 10) & 1) != 0)
156    }
157    #[doc = "Bit 11 - ASYNCH11 pin enable control bit"]
158    #[inline(always)]
159    pub fn asynch11pen(&self) -> ASYNCH11PEN_R {
160        ASYNCH11PEN_R::new(((self.bits >> 11) & 1) != 0)
161    }
162    #[doc = "Bit 12 - SYNCH0 pin enable control bit"]
163    #[inline(always)]
164    pub fn synch0pen(&self) -> SYNCH0PEN_R {
165        SYNCH0PEN_R::new(((self.bits >> 12) & 1) != 0)
166    }
167    #[doc = "Bit 13 - SYNCH1 pin enable control bit"]
168    #[inline(always)]
169    pub fn synch1pen(&self) -> SYNCH1PEN_R {
170        SYNCH1PEN_R::new(((self.bits >> 13) & 1) != 0)
171    }
172    #[doc = "Bit 14 - SYNCH2 pin enable control bit"]
173    #[inline(always)]
174    pub fn synch2pen(&self) -> SYNCH2PEN_R {
175        SYNCH2PEN_R::new(((self.bits >> 14) & 1) != 0)
176    }
177    #[doc = "Bit 15 - SYNCH3 pin enable control bit"]
178    #[inline(always)]
179    pub fn synch3pen(&self) -> SYNCH3PEN_R {
180        SYNCH3PEN_R::new(((self.bits >> 15) & 1) != 0)
181    }
182}
183impl W {
184    #[doc = "Bit 0 - ASYNCH0 pin enable control bit"]
185    #[inline(always)]
186    #[must_use]
187    pub fn asynch0pen(&mut self) -> ASYNCH0PEN_W<0> {
188        ASYNCH0PEN_W::new(self)
189    }
190    #[doc = "Bit 1 - ASYNCH1 pin enable control bit"]
191    #[inline(always)]
192    #[must_use]
193    pub fn asynch1pen(&mut self) -> ASYNCH1PEN_W<1> {
194        ASYNCH1PEN_W::new(self)
195    }
196    #[doc = "Bit 2 - ASYNCH2 pin enable control bit"]
197    #[inline(always)]
198    #[must_use]
199    pub fn asynch2pen(&mut self) -> ASYNCH2PEN_W<2> {
200        ASYNCH2PEN_W::new(self)
201    }
202    #[doc = "Bit 3 - ASYNCH3 pin enable control bit"]
203    #[inline(always)]
204    #[must_use]
205    pub fn asynch3pen(&mut self) -> ASYNCH3PEN_W<3> {
206        ASYNCH3PEN_W::new(self)
207    }
208    #[doc = "Bit 4 - ASYNCH4 pin enable control bit"]
209    #[inline(always)]
210    #[must_use]
211    pub fn asynch4pen(&mut self) -> ASYNCH4PEN_W<4> {
212        ASYNCH4PEN_W::new(self)
213    }
214    #[doc = "Bit 5 - ASYNCH5 pin enable control bit"]
215    #[inline(always)]
216    #[must_use]
217    pub fn asynch5pen(&mut self) -> ASYNCH5PEN_W<5> {
218        ASYNCH5PEN_W::new(self)
219    }
220    #[doc = "Bit 6 - ASYNCH6 pin enable control bit"]
221    #[inline(always)]
222    #[must_use]
223    pub fn asynch6pen(&mut self) -> ASYNCH6PEN_W<6> {
224        ASYNCH6PEN_W::new(self)
225    }
226    #[doc = "Bit 7 - ASYNCH7 pin enable control bit"]
227    #[inline(always)]
228    #[must_use]
229    pub fn asynch7pen(&mut self) -> ASYNCH7PEN_W<7> {
230        ASYNCH7PEN_W::new(self)
231    }
232    #[doc = "Bit 8 - ASYNCH8 pin enable control bit"]
233    #[inline(always)]
234    #[must_use]
235    pub fn asynch8pen(&mut self) -> ASYNCH8PEN_W<8> {
236        ASYNCH8PEN_W::new(self)
237    }
238    #[doc = "Bit 9 - ASYNCH9 pin enable control bit"]
239    #[inline(always)]
240    #[must_use]
241    pub fn asynch9pen(&mut self) -> ASYNCH9PEN_W<9> {
242        ASYNCH9PEN_W::new(self)
243    }
244    #[doc = "Bit 10 - ASYNCH10 pin enable control bit"]
245    #[inline(always)]
246    #[must_use]
247    pub fn asynch10pen(&mut self) -> ASYNCH10PEN_W<10> {
248        ASYNCH10PEN_W::new(self)
249    }
250    #[doc = "Bit 11 - ASYNCH11 pin enable control bit"]
251    #[inline(always)]
252    #[must_use]
253    pub fn asynch11pen(&mut self) -> ASYNCH11PEN_W<11> {
254        ASYNCH11PEN_W::new(self)
255    }
256    #[doc = "Bit 12 - SYNCH0 pin enable control bit"]
257    #[inline(always)]
258    #[must_use]
259    pub fn synch0pen(&mut self) -> SYNCH0PEN_W<12> {
260        SYNCH0PEN_W::new(self)
261    }
262    #[doc = "Bit 13 - SYNCH1 pin enable control bit"]
263    #[inline(always)]
264    #[must_use]
265    pub fn synch1pen(&mut self) -> SYNCH1PEN_W<13> {
266        SYNCH1PEN_W::new(self)
267    }
268    #[doc = "Bit 14 - SYNCH2 pin enable control bit"]
269    #[inline(always)]
270    #[must_use]
271    pub fn synch2pen(&mut self) -> SYNCH2PEN_W<14> {
272        SYNCH2PEN_W::new(self)
273    }
274    #[doc = "Bit 15 - SYNCH3 pin enable control bit"]
275    #[inline(always)]
276    #[must_use]
277    pub fn synch3pen(&mut self) -> SYNCH3PEN_W<15> {
278        SYNCH3PEN_W::new(self)
279    }
280    #[doc = "Writes raw bits to the register."]
281    #[inline(always)]
282    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
283        self.0.bits(bits);
284        self
285    }
286}
287#[doc = "PRS0 pin enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prs0_routeen](index.html) module"]
288pub struct PRS0_ROUTEEN_SPEC;
289impl crate::RegisterSpec for PRS0_ROUTEEN_SPEC {
290    type Ux = u32;
291}
292#[doc = "`read()` method returns [prs0_routeen::R](R) reader structure"]
293impl crate::Readable for PRS0_ROUTEEN_SPEC {
294    type Reader = R;
295}
296#[doc = "`write(|w| ..)` method takes [prs0_routeen::W](W) writer structure"]
297impl crate::Writable for PRS0_ROUTEEN_SPEC {
298    type Writer = W;
299    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
300    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
301}
302#[doc = "`reset()` method sets PRS0_ROUTEEN to value 0"]
303impl crate::Resettable for PRS0_ROUTEEN_SPEC {
304    const RESET_VALUE: Self::Ux = 0;
305}
efm32pg22_pac/efm32pg22c200/gpio_s/prs0_routeen.rs

efm32pg22_pac/efm32pg22c200/gpio_s/
prs0_routeen.rs
