efm32pg22_pac/efm32pg22c200/gpio_s/
extipselh.rs

1#[doc = "Register `EXTIPSELH` reader"]
2pub struct R(crate::R<EXTIPSELH_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<EXTIPSELH_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<EXTIPSELH_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<EXTIPSELH_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `EXTIPSELH` writer"]
17pub struct W(crate::W<EXTIPSELH_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<EXTIPSELH_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<EXTIPSELH_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<EXTIPSELH_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `EXTIPSEL0` reader - External Interrupt Port Select"]
38pub type EXTIPSEL0_R = crate::FieldReader<u8, EXTIPSEL0_A>;
39#[doc = "External Interrupt Port Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum EXTIPSEL0_A {
43    #[doc = "0: Port A group selected"]
44    PORTA = 0,
45    #[doc = "1: Port B group selected"]
46    PORTB = 1,
47    #[doc = "2: Port C group selected"]
48    PORTC = 2,
49    #[doc = "3: Port D group selected"]
50    PORTD = 3,
51}
52impl From<EXTIPSEL0_A> for u8 {
53    #[inline(always)]
54    fn from(variant: EXTIPSEL0_A) -> Self {
55        variant as _
56    }
57}
58impl EXTIPSEL0_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> EXTIPSEL0_A {
62        match self.bits {
63            0 => EXTIPSEL0_A::PORTA,
64            1 => EXTIPSEL0_A::PORTB,
65            2 => EXTIPSEL0_A::PORTC,
66            3 => EXTIPSEL0_A::PORTD,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `PORTA`"]
71    #[inline(always)]
72    pub fn is_porta(&self) -> bool {
73        *self == EXTIPSEL0_A::PORTA
74    }
75    #[doc = "Checks if the value of the field is `PORTB`"]
76    #[inline(always)]
77    pub fn is_portb(&self) -> bool {
78        *self == EXTIPSEL0_A::PORTB
79    }
80    #[doc = "Checks if the value of the field is `PORTC`"]
81    #[inline(always)]
82    pub fn is_portc(&self) -> bool {
83        *self == EXTIPSEL0_A::PORTC
84    }
85    #[doc = "Checks if the value of the field is `PORTD`"]
86    #[inline(always)]
87    pub fn is_portd(&self) -> bool {
88        *self == EXTIPSEL0_A::PORTD
89    }
90}
91#[doc = "Field `EXTIPSEL0` writer - External Interrupt Port Select"]
92pub type EXTIPSEL0_W<'a, const O: u8> =
93    crate::FieldWriterSafe<'a, u32, EXTIPSELH_SPEC, u8, EXTIPSEL0_A, 2, O>;
94impl<'a, const O: u8> EXTIPSEL0_W<'a, O> {
95    #[doc = "Port A group selected"]
96    #[inline(always)]
97    pub fn porta(self) -> &'a mut W {
98        self.variant(EXTIPSEL0_A::PORTA)
99    }
100    #[doc = "Port B group selected"]
101    #[inline(always)]
102    pub fn portb(self) -> &'a mut W {
103        self.variant(EXTIPSEL0_A::PORTB)
104    }
105    #[doc = "Port C group selected"]
106    #[inline(always)]
107    pub fn portc(self) -> &'a mut W {
108        self.variant(EXTIPSEL0_A::PORTC)
109    }
110    #[doc = "Port D group selected"]
111    #[inline(always)]
112    pub fn portd(self) -> &'a mut W {
113        self.variant(EXTIPSEL0_A::PORTD)
114    }
115}
116#[doc = "Field `EXTIPSEL1` reader - External Interrupt Port Select"]
117pub type EXTIPSEL1_R = crate::FieldReader<u8, EXTIPSEL1_A>;
118#[doc = "External Interrupt Port Select\n\nValue on reset: 0"]
119#[derive(Clone, Copy, Debug, PartialEq, Eq)]
120#[repr(u8)]
121pub enum EXTIPSEL1_A {
122    #[doc = "0: Port A group selected"]
123    PORTA = 0,
124    #[doc = "1: Port B group selected"]
125    PORTB = 1,
126    #[doc = "2: Port C group selected"]
127    PORTC = 2,
128    #[doc = "3: Port D group selected"]
129    PORTD = 3,
130}
131impl From<EXTIPSEL1_A> for u8 {
132    #[inline(always)]
133    fn from(variant: EXTIPSEL1_A) -> Self {
134        variant as _
135    }
136}
137impl EXTIPSEL1_R {
138    #[doc = "Get enumerated values variant"]
139    #[inline(always)]
140    pub fn variant(&self) -> EXTIPSEL1_A {
141        match self.bits {
142            0 => EXTIPSEL1_A::PORTA,
143            1 => EXTIPSEL1_A::PORTB,
144            2 => EXTIPSEL1_A::PORTC,
145            3 => EXTIPSEL1_A::PORTD,
146            _ => unreachable!(),
147        }
148    }
149    #[doc = "Checks if the value of the field is `PORTA`"]
150    #[inline(always)]
151    pub fn is_porta(&self) -> bool {
152        *self == EXTIPSEL1_A::PORTA
153    }
154    #[doc = "Checks if the value of the field is `PORTB`"]
155    #[inline(always)]
156    pub fn is_portb(&self) -> bool {
157        *self == EXTIPSEL1_A::PORTB
158    }
159    #[doc = "Checks if the value of the field is `PORTC`"]
160    #[inline(always)]
161    pub fn is_portc(&self) -> bool {
162        *self == EXTIPSEL1_A::PORTC
163    }
164    #[doc = "Checks if the value of the field is `PORTD`"]
165    #[inline(always)]
166    pub fn is_portd(&self) -> bool {
167        *self == EXTIPSEL1_A::PORTD
168    }
169}
170#[doc = "Field `EXTIPSEL1` writer - External Interrupt Port Select"]
171pub type EXTIPSEL1_W<'a, const O: u8> =
172    crate::FieldWriterSafe<'a, u32, EXTIPSELH_SPEC, u8, EXTIPSEL1_A, 2, O>;
173impl<'a, const O: u8> EXTIPSEL1_W<'a, O> {
174    #[doc = "Port A group selected"]
175    #[inline(always)]
176    pub fn porta(self) -> &'a mut W {
177        self.variant(EXTIPSEL1_A::PORTA)
178    }
179    #[doc = "Port B group selected"]
180    #[inline(always)]
181    pub fn portb(self) -> &'a mut W {
182        self.variant(EXTIPSEL1_A::PORTB)
183    }
184    #[doc = "Port C group selected"]
185    #[inline(always)]
186    pub fn portc(self) -> &'a mut W {
187        self.variant(EXTIPSEL1_A::PORTC)
188    }
189    #[doc = "Port D group selected"]
190    #[inline(always)]
191    pub fn portd(self) -> &'a mut W {
192        self.variant(EXTIPSEL1_A::PORTD)
193    }
194}
195#[doc = "Field `EXTIPSEL2` reader - External Interrupt Port Select"]
196pub type EXTIPSEL2_R = crate::FieldReader<u8, EXTIPSEL2_A>;
197#[doc = "External Interrupt Port Select\n\nValue on reset: 0"]
198#[derive(Clone, Copy, Debug, PartialEq, Eq)]
199#[repr(u8)]
200pub enum EXTIPSEL2_A {
201    #[doc = "0: Port A group selected"]
202    PORTA = 0,
203    #[doc = "1: Port B group selected"]
204    PORTB = 1,
205    #[doc = "2: Port C group selected"]
206    PORTC = 2,
207    #[doc = "3: Port D group selected"]
208    PORTD = 3,
209}
210impl From<EXTIPSEL2_A> for u8 {
211    #[inline(always)]
212    fn from(variant: EXTIPSEL2_A) -> Self {
213        variant as _
214    }
215}
216impl EXTIPSEL2_R {
217    #[doc = "Get enumerated values variant"]
218    #[inline(always)]
219    pub fn variant(&self) -> EXTIPSEL2_A {
220        match self.bits {
221            0 => EXTIPSEL2_A::PORTA,
222            1 => EXTIPSEL2_A::PORTB,
223            2 => EXTIPSEL2_A::PORTC,
224            3 => EXTIPSEL2_A::PORTD,
225            _ => unreachable!(),
226        }
227    }
228    #[doc = "Checks if the value of the field is `PORTA`"]
229    #[inline(always)]
230    pub fn is_porta(&self) -> bool {
231        *self == EXTIPSEL2_A::PORTA
232    }
233    #[doc = "Checks if the value of the field is `PORTB`"]
234    #[inline(always)]
235    pub fn is_portb(&self) -> bool {
236        *self == EXTIPSEL2_A::PORTB
237    }
238    #[doc = "Checks if the value of the field is `PORTC`"]
239    #[inline(always)]
240    pub fn is_portc(&self) -> bool {
241        *self == EXTIPSEL2_A::PORTC
242    }
243    #[doc = "Checks if the value of the field is `PORTD`"]
244    #[inline(always)]
245    pub fn is_portd(&self) -> bool {
246        *self == EXTIPSEL2_A::PORTD
247    }
248}
249#[doc = "Field `EXTIPSEL2` writer - External Interrupt Port Select"]
250pub type EXTIPSEL2_W<'a, const O: u8> =
251    crate::FieldWriterSafe<'a, u32, EXTIPSELH_SPEC, u8, EXTIPSEL2_A, 2, O>;
252impl<'a, const O: u8> EXTIPSEL2_W<'a, O> {
253    #[doc = "Port A group selected"]
254    #[inline(always)]
255    pub fn porta(self) -> &'a mut W {
256        self.variant(EXTIPSEL2_A::PORTA)
257    }
258    #[doc = "Port B group selected"]
259    #[inline(always)]
260    pub fn portb(self) -> &'a mut W {
261        self.variant(EXTIPSEL2_A::PORTB)
262    }
263    #[doc = "Port C group selected"]
264    #[inline(always)]
265    pub fn portc(self) -> &'a mut W {
266        self.variant(EXTIPSEL2_A::PORTC)
267    }
268    #[doc = "Port D group selected"]
269    #[inline(always)]
270    pub fn portd(self) -> &'a mut W {
271        self.variant(EXTIPSEL2_A::PORTD)
272    }
273}
274#[doc = "Field `EXTIPSEL3` reader - External Interrupt Port Select"]
275pub type EXTIPSEL3_R = crate::FieldReader<u8, EXTIPSEL3_A>;
276#[doc = "External Interrupt Port Select\n\nValue on reset: 0"]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278#[repr(u8)]
279pub enum EXTIPSEL3_A {
280    #[doc = "0: Port A group selected"]
281    PORTA = 0,
282    #[doc = "1: Port B group selected"]
283    PORTB = 1,
284    #[doc = "2: Port C group selected"]
285    PORTC = 2,
286    #[doc = "3: Port D group selected"]
287    PORTD = 3,
288}
289impl From<EXTIPSEL3_A> for u8 {
290    #[inline(always)]
291    fn from(variant: EXTIPSEL3_A) -> Self {
292        variant as _
293    }
294}
295impl EXTIPSEL3_R {
296    #[doc = "Get enumerated values variant"]
297    #[inline(always)]
298    pub fn variant(&self) -> EXTIPSEL3_A {
299        match self.bits {
300            0 => EXTIPSEL3_A::PORTA,
301            1 => EXTIPSEL3_A::PORTB,
302            2 => EXTIPSEL3_A::PORTC,
303            3 => EXTIPSEL3_A::PORTD,
304            _ => unreachable!(),
305        }
306    }
307    #[doc = "Checks if the value of the field is `PORTA`"]
308    #[inline(always)]
309    pub fn is_porta(&self) -> bool {
310        *self == EXTIPSEL3_A::PORTA
311    }
312    #[doc = "Checks if the value of the field is `PORTB`"]
313    #[inline(always)]
314    pub fn is_portb(&self) -> bool {
315        *self == EXTIPSEL3_A::PORTB
316    }
317    #[doc = "Checks if the value of the field is `PORTC`"]
318    #[inline(always)]
319    pub fn is_portc(&self) -> bool {
320        *self == EXTIPSEL3_A::PORTC
321    }
322    #[doc = "Checks if the value of the field is `PORTD`"]
323    #[inline(always)]
324    pub fn is_portd(&self) -> bool {
325        *self == EXTIPSEL3_A::PORTD
326    }
327}
328#[doc = "Field `EXTIPSEL3` writer - External Interrupt Port Select"]
329pub type EXTIPSEL3_W<'a, const O: u8> =
330    crate::FieldWriterSafe<'a, u32, EXTIPSELH_SPEC, u8, EXTIPSEL3_A, 2, O>;
331impl<'a, const O: u8> EXTIPSEL3_W<'a, O> {
332    #[doc = "Port A group selected"]
333    #[inline(always)]
334    pub fn porta(self) -> &'a mut W {
335        self.variant(EXTIPSEL3_A::PORTA)
336    }
337    #[doc = "Port B group selected"]
338    #[inline(always)]
339    pub fn portb(self) -> &'a mut W {
340        self.variant(EXTIPSEL3_A::PORTB)
341    }
342    #[doc = "Port C group selected"]
343    #[inline(always)]
344    pub fn portc(self) -> &'a mut W {
345        self.variant(EXTIPSEL3_A::PORTC)
346    }
347    #[doc = "Port D group selected"]
348    #[inline(always)]
349    pub fn portd(self) -> &'a mut W {
350        self.variant(EXTIPSEL3_A::PORTD)
351    }
352}
353impl R {
354    #[doc = "Bits 0:1 - External Interrupt Port Select"]
355    #[inline(always)]
356    pub fn extipsel0(&self) -> EXTIPSEL0_R {
357        EXTIPSEL0_R::new((self.bits & 3) as u8)
358    }
359    #[doc = "Bits 4:5 - External Interrupt Port Select"]
360    #[inline(always)]
361    pub fn extipsel1(&self) -> EXTIPSEL1_R {
362        EXTIPSEL1_R::new(((self.bits >> 4) & 3) as u8)
363    }
364    #[doc = "Bits 8:9 - External Interrupt Port Select"]
365    #[inline(always)]
366    pub fn extipsel2(&self) -> EXTIPSEL2_R {
367        EXTIPSEL2_R::new(((self.bits >> 8) & 3) as u8)
368    }
369    #[doc = "Bits 12:13 - External Interrupt Port Select"]
370    #[inline(always)]
371    pub fn extipsel3(&self) -> EXTIPSEL3_R {
372        EXTIPSEL3_R::new(((self.bits >> 12) & 3) as u8)
373    }
374}
375impl W {
376    #[doc = "Bits 0:1 - External Interrupt Port Select"]
377    #[inline(always)]
378    #[must_use]
379    pub fn extipsel0(&mut self) -> EXTIPSEL0_W<0> {
380        EXTIPSEL0_W::new(self)
381    }
382    #[doc = "Bits 4:5 - External Interrupt Port Select"]
383    #[inline(always)]
384    #[must_use]
385    pub fn extipsel1(&mut self) -> EXTIPSEL1_W<4> {
386        EXTIPSEL1_W::new(self)
387    }
388    #[doc = "Bits 8:9 - External Interrupt Port Select"]
389    #[inline(always)]
390    #[must_use]
391    pub fn extipsel2(&mut self) -> EXTIPSEL2_W<8> {
392        EXTIPSEL2_W::new(self)
393    }
394    #[doc = "Bits 12:13 - External Interrupt Port Select"]
395    #[inline(always)]
396    #[must_use]
397    pub fn extipsel3(&mut self) -> EXTIPSEL3_W<12> {
398        EXTIPSEL3_W::new(self)
399    }
400    #[doc = "Writes raw bits to the register."]
401    #[inline(always)]
402    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
403        self.0.bits(bits);
404        self
405    }
406}
407#[doc = "External interrupt Port Select High\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extipselh](index.html) module"]
408pub struct EXTIPSELH_SPEC;
409impl crate::RegisterSpec for EXTIPSELH_SPEC {
410    type Ux = u32;
411}
412#[doc = "`read()` method returns [extipselh::R](R) reader structure"]
413impl crate::Readable for EXTIPSELH_SPEC {
414    type Reader = R;
415}
416#[doc = "`write(|w| ..)` method takes [extipselh::W](W) writer structure"]
417impl crate::Writable for EXTIPSELH_SPEC {
418    type Writer = W;
419    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
420    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
421}
422#[doc = "`reset()` method sets EXTIPSELH to value 0"]
423impl crate::Resettable for EXTIPSELH_SPEC {
424    const RESET_VALUE: Self::Ux = 0;
425}
efm32pg22_pac/efm32pg22c200/gpio_s/extipselh.rs

efm32pg22_pac/efm32pg22c200/gpio_s/
extipselh.rs
