efm32pg22_pac/efm32pg22c200/gpio_ns/
usart0_routeen.rs

1#[doc = "Register `USART0_ROUTEEN` reader"]
2pub struct R(crate::R<USART0_ROUTEEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<USART0_ROUTEEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<USART0_ROUTEEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<USART0_ROUTEEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `USART0_ROUTEEN` writer"]
17pub struct W(crate::W<USART0_ROUTEEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<USART0_ROUTEEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<USART0_ROUTEEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<USART0_ROUTEEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CSPEN` reader - CS pin enable control bit"]
38pub type CSPEN_R = crate::BitReader<bool>;
39#[doc = "Field `CSPEN` writer - CS pin enable control bit"]
40pub type CSPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, USART0_ROUTEEN_SPEC, bool, O>;
41#[doc = "Field `RTSPEN` reader - RTS pin enable control bit"]
42pub type RTSPEN_R = crate::BitReader<bool>;
43#[doc = "Field `RTSPEN` writer - RTS pin enable control bit"]
44pub type RTSPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, USART0_ROUTEEN_SPEC, bool, O>;
45#[doc = "Field `RXPEN` reader - RX pin enable control bit"]
46pub type RXPEN_R = crate::BitReader<bool>;
47#[doc = "Field `RXPEN` writer - RX pin enable control bit"]
48pub type RXPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, USART0_ROUTEEN_SPEC, bool, O>;
49#[doc = "Field `CLKPEN` reader - SCLK pin enable control bit"]
50pub type CLKPEN_R = crate::BitReader<bool>;
51#[doc = "Field `CLKPEN` writer - SCLK pin enable control bit"]
52pub type CLKPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, USART0_ROUTEEN_SPEC, bool, O>;
53#[doc = "Field `TXPEN` reader - TX pin enable control bit"]
54pub type TXPEN_R = crate::BitReader<bool>;
55#[doc = "Field `TXPEN` writer - TX pin enable control bit"]
56pub type TXPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, USART0_ROUTEEN_SPEC, bool, O>;
57impl R {
58    #[doc = "Bit 0 - CS pin enable control bit"]
59    #[inline(always)]
60    pub fn cspen(&self) -> CSPEN_R {
61        CSPEN_R::new((self.bits & 1) != 0)
62    }
63    #[doc = "Bit 1 - RTS pin enable control bit"]
64    #[inline(always)]
65    pub fn rtspen(&self) -> RTSPEN_R {
66        RTSPEN_R::new(((self.bits >> 1) & 1) != 0)
67    }
68    #[doc = "Bit 2 - RX pin enable control bit"]
69    #[inline(always)]
70    pub fn rxpen(&self) -> RXPEN_R {
71        RXPEN_R::new(((self.bits >> 2) & 1) != 0)
72    }
73    #[doc = "Bit 3 - SCLK pin enable control bit"]
74    #[inline(always)]
75    pub fn clkpen(&self) -> CLKPEN_R {
76        CLKPEN_R::new(((self.bits >> 3) & 1) != 0)
77    }
78    #[doc = "Bit 4 - TX pin enable control bit"]
79    #[inline(always)]
80    pub fn txpen(&self) -> TXPEN_R {
81        TXPEN_R::new(((self.bits >> 4) & 1) != 0)
82    }
83}
84impl W {
85    #[doc = "Bit 0 - CS pin enable control bit"]
86    #[inline(always)]
87    #[must_use]
88    pub fn cspen(&mut self) -> CSPEN_W<0> {
89        CSPEN_W::new(self)
90    }
91    #[doc = "Bit 1 - RTS pin enable control bit"]
92    #[inline(always)]
93    #[must_use]
94    pub fn rtspen(&mut self) -> RTSPEN_W<1> {
95        RTSPEN_W::new(self)
96    }
97    #[doc = "Bit 2 - RX pin enable control bit"]
98    #[inline(always)]
99    #[must_use]
100    pub fn rxpen(&mut self) -> RXPEN_W<2> {
101        RXPEN_W::new(self)
102    }
103    #[doc = "Bit 3 - SCLK pin enable control bit"]
104    #[inline(always)]
105    #[must_use]
106    pub fn clkpen(&mut self) -> CLKPEN_W<3> {
107        CLKPEN_W::new(self)
108    }
109    #[doc = "Bit 4 - TX pin enable control bit"]
110    #[inline(always)]
111    #[must_use]
112    pub fn txpen(&mut self) -> TXPEN_W<4> {
113        TXPEN_W::new(self)
114    }
115    #[doc = "Writes raw bits to the register."]
116    #[inline(always)]
117    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
118        self.0.bits(bits);
119        self
120    }
121}
122#[doc = "USART0 pin enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usart0_routeen](index.html) module"]
123pub struct USART0_ROUTEEN_SPEC;
124impl crate::RegisterSpec for USART0_ROUTEEN_SPEC {
125    type Ux = u32;
126}
127#[doc = "`read()` method returns [usart0_routeen::R](R) reader structure"]
128impl crate::Readable for USART0_ROUTEEN_SPEC {
129    type Reader = R;
130}
131#[doc = "`write(|w| ..)` method takes [usart0_routeen::W](W) writer structure"]
132impl crate::Writable for USART0_ROUTEEN_SPEC {
133    type Writer = W;
134    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
135    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
136}
137#[doc = "`reset()` method sets USART0_ROUTEEN to value 0"]
138impl crate::Resettable for USART0_ROUTEEN_SPEC {
139    const RESET_VALUE: Self::Ux = 0;
140}
efm32pg22_pac/efm32pg22c200/gpio_ns/usart0_routeen.rs

efm32pg22_pac/efm32pg22c200/gpio_ns/
usart0_routeen.rs
