efm32pg22_pac/efm32pg22c200/gpio_ns/
letimer0_out1route.rs

1#[doc = "Register `LETIMER0_OUT1ROUTE` reader"]
2pub struct R(crate::R<LETIMER0_OUT1ROUTE_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<LETIMER0_OUT1ROUTE_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<LETIMER0_OUT1ROUTE_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<LETIMER0_OUT1ROUTE_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `LETIMER0_OUT1ROUTE` writer"]
17pub struct W(crate::W<LETIMER0_OUT1ROUTE_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<LETIMER0_OUT1ROUTE_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<LETIMER0_OUT1ROUTE_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<LETIMER0_OUT1ROUTE_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PORT` reader - OUT1 port select register"]
38pub type PORT_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `PORT` writer - OUT1 port select register"]
40pub type PORT_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, LETIMER0_OUT1ROUTE_SPEC, u8, u8, 2, O>;
42#[doc = "Field `PIN` reader - OUT1 pin select register"]
43pub type PIN_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `PIN` writer - OUT1 pin select register"]
45pub type PIN_W<'a, const O: u8> =
46    crate::FieldWriter<'a, u32, LETIMER0_OUT1ROUTE_SPEC, u8, u8, 4, O>;
47impl R {
48    #[doc = "Bits 0:1 - OUT1 port select register"]
49    #[inline(always)]
50    pub fn port(&self) -> PORT_R {
51        PORT_R::new((self.bits & 3) as u8)
52    }
53    #[doc = "Bits 16:19 - OUT1 pin select register"]
54    #[inline(always)]
55    pub fn pin(&self) -> PIN_R {
56        PIN_R::new(((self.bits >> 16) & 0x0f) as u8)
57    }
58}
59impl W {
60    #[doc = "Bits 0:1 - OUT1 port select register"]
61    #[inline(always)]
62    #[must_use]
63    pub fn port(&mut self) -> PORT_W<0> {
64        PORT_W::new(self)
65    }
66    #[doc = "Bits 16:19 - OUT1 pin select register"]
67    #[inline(always)]
68    #[must_use]
69    pub fn pin(&mut self) -> PIN_W<16> {
70        PIN_W::new(self)
71    }
72    #[doc = "Writes raw bits to the register."]
73    #[inline(always)]
74    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
75        self.0.bits(bits);
76        self
77    }
78}
79#[doc = "OUT1 port/pin select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [letimer0_out1route](index.html) module"]
80pub struct LETIMER0_OUT1ROUTE_SPEC;
81impl crate::RegisterSpec for LETIMER0_OUT1ROUTE_SPEC {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [letimer0_out1route::R](R) reader structure"]
85impl crate::Readable for LETIMER0_OUT1ROUTE_SPEC {
86    type Reader = R;
87}
88#[doc = "`write(|w| ..)` method takes [letimer0_out1route::W](W) writer structure"]
89impl crate::Writable for LETIMER0_OUT1ROUTE_SPEC {
90    type Writer = W;
91    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
92    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
93}
94#[doc = "`reset()` method sets LETIMER0_OUT1ROUTE to value 0"]
95impl crate::Resettable for LETIMER0_OUT1ROUTE_SPEC {
96    const RESET_VALUE: Self::Ux = 0;
97}
efm32pg22_pac/efm32pg22c200/gpio_ns/letimer0_out1route.rs

efm32pg22_pac/efm32pg22c200/gpio_ns/
letimer0_out1route.rs
