efm32pg22_pac/efm32pg22c200/euart0_ns/
timingcfg.rs

1#[doc = "Register `TIMINGCFG` reader"]
2pub struct R(crate::R<TIMINGCFG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<TIMINGCFG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<TIMINGCFG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<TIMINGCFG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `TIMINGCFG` writer"]
17pub struct W(crate::W<TIMINGCFG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<TIMINGCFG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<TIMINGCFG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<TIMINGCFG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TXDELAY` reader - TX Delay Transmission"]
38pub type TXDELAY_R = crate::FieldReader<u8, TXDELAY_A>;
39#[doc = "TX Delay Transmission\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum TXDELAY_A {
43    #[doc = "0: Frames are transmitted immediately."]
44    NONE = 0,
45    #[doc = "1: Transmission of new frames is delayed by a single bit period."]
46    SINGLE = 1,
47    #[doc = "2: Transmission of new frames is delayed by a two bit periods."]
48    DOUBLE = 2,
49    #[doc = "3: Transmission of new frames is delayed by a three bit periods."]
50    TRIPPLE = 3,
51}
52impl From<TXDELAY_A> for u8 {
53    #[inline(always)]
54    fn from(variant: TXDELAY_A) -> Self {
55        variant as _
56    }
57}
58impl TXDELAY_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> TXDELAY_A {
62        match self.bits {
63            0 => TXDELAY_A::NONE,
64            1 => TXDELAY_A::SINGLE,
65            2 => TXDELAY_A::DOUBLE,
66            3 => TXDELAY_A::TRIPPLE,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `NONE`"]
71    #[inline(always)]
72    pub fn is_none(&self) -> bool {
73        *self == TXDELAY_A::NONE
74    }
75    #[doc = "Checks if the value of the field is `SINGLE`"]
76    #[inline(always)]
77    pub fn is_single(&self) -> bool {
78        *self == TXDELAY_A::SINGLE
79    }
80    #[doc = "Checks if the value of the field is `DOUBLE`"]
81    #[inline(always)]
82    pub fn is_double(&self) -> bool {
83        *self == TXDELAY_A::DOUBLE
84    }
85    #[doc = "Checks if the value of the field is `TRIPPLE`"]
86    #[inline(always)]
87    pub fn is_tripple(&self) -> bool {
88        *self == TXDELAY_A::TRIPPLE
89    }
90}
91#[doc = "Field `TXDELAY` writer - TX Delay Transmission"]
92pub type TXDELAY_W<'a, const O: u8> =
93    crate::FieldWriterSafe<'a, u32, TIMINGCFG_SPEC, u8, TXDELAY_A, 2, O>;
94impl<'a, const O: u8> TXDELAY_W<'a, O> {
95    #[doc = "Frames are transmitted immediately."]
96    #[inline(always)]
97    pub fn none(self) -> &'a mut W {
98        self.variant(TXDELAY_A::NONE)
99    }
100    #[doc = "Transmission of new frames is delayed by a single bit period."]
101    #[inline(always)]
102    pub fn single(self) -> &'a mut W {
103        self.variant(TXDELAY_A::SINGLE)
104    }
105    #[doc = "Transmission of new frames is delayed by a two bit periods."]
106    #[inline(always)]
107    pub fn double(self) -> &'a mut W {
108        self.variant(TXDELAY_A::DOUBLE)
109    }
110    #[doc = "Transmission of new frames is delayed by a three bit periods."]
111    #[inline(always)]
112    pub fn tripple(self) -> &'a mut W {
113        self.variant(TXDELAY_A::TRIPPLE)
114    }
115}
116impl R {
117    #[doc = "Bits 0:1 - TX Delay Transmission"]
118    #[inline(always)]
119    pub fn txdelay(&self) -> TXDELAY_R {
120        TXDELAY_R::new((self.bits & 3) as u8)
121    }
122}
123impl W {
124    #[doc = "Bits 0:1 - TX Delay Transmission"]
125    #[inline(always)]
126    #[must_use]
127    pub fn txdelay(&mut self) -> TXDELAY_W<0> {
128        TXDELAY_W::new(self)
129    }
130    #[doc = "Writes raw bits to the register."]
131    #[inline(always)]
132    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
133        self.0.bits(bits);
134        self
135    }
136}
137#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timingcfg](index.html) module"]
138pub struct TIMINGCFG_SPEC;
139impl crate::RegisterSpec for TIMINGCFG_SPEC {
140    type Ux = u32;
141}
142#[doc = "`read()` method returns [timingcfg::R](R) reader structure"]
143impl crate::Readable for TIMINGCFG_SPEC {
144    type Reader = R;
145}
146#[doc = "`write(|w| ..)` method takes [timingcfg::W](W) writer structure"]
147impl crate::Writable for TIMINGCFG_SPEC {
148    type Writer = W;
149    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
150    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
151}
152#[doc = "`reset()` method sets TIMINGCFG to value 0"]
153impl crate::Resettable for TIMINGCFG_SPEC {
154    const RESET_VALUE: Self::Ux = 0;
155}
efm32pg22_pac/efm32pg22c200/euart0_ns/timingcfg.rs

efm32pg22_pac/efm32pg22c200/euart0_ns/
timingcfg.rs
