efm32pg22_pac/efm32pg22c200/euart0_ns/
cfg1.rs

1#[doc = "Register `CFG1` reader"]
2pub struct R(crate::R<CFG1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CFG1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CFG1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CFG1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CFG1` writer"]
17pub struct W(crate::W<CFG1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CFG1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CFG1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CFG1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DBGHALT` reader - Debug halt"]
38pub type DBGHALT_R = crate::BitReader<DBGHALT_A>;
39#[doc = "Debug halt\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum DBGHALT_A {
42    #[doc = "0: Continue normal UART operation even if core is halted"]
43    DISABLE = 0,
44    #[doc = "1: If core is halted, receive one frame and then halt reception by deactivating RTS. Next frame reception happens when the core is unhalted during single stepping."]
45    ENABLE = 1,
46}
47impl From<DBGHALT_A> for bool {
48    #[inline(always)]
49    fn from(variant: DBGHALT_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl DBGHALT_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> DBGHALT_A {
57        match self.bits {
58            false => DBGHALT_A::DISABLE,
59            true => DBGHALT_A::ENABLE,
60        }
61    }
62    #[doc = "Checks if the value of the field is `DISABLE`"]
63    #[inline(always)]
64    pub fn is_disable(&self) -> bool {
65        *self == DBGHALT_A::DISABLE
66    }
67    #[doc = "Checks if the value of the field is `ENABLE`"]
68    #[inline(always)]
69    pub fn is_enable(&self) -> bool {
70        *self == DBGHALT_A::ENABLE
71    }
72}
73#[doc = "Field `DBGHALT` writer - Debug halt"]
74pub type DBGHALT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG1_SPEC, DBGHALT_A, O>;
75impl<'a, const O: u8> DBGHALT_W<'a, O> {
76    #[doc = "Continue normal UART operation even if core is halted"]
77    #[inline(always)]
78    pub fn disable(self) -> &'a mut W {
79        self.variant(DBGHALT_A::DISABLE)
80    }
81    #[doc = "If core is halted, receive one frame and then halt reception by deactivating RTS. Next frame reception happens when the core is unhalted during single stepping."]
82    #[inline(always)]
83    pub fn enable(self) -> &'a mut W {
84        self.variant(DBGHALT_A::ENABLE)
85    }
86}
87#[doc = "Field `CTSINV` reader - Clear-to-send Invert Enable"]
88pub type CTSINV_R = crate::BitReader<CTSINV_A>;
89#[doc = "Clear-to-send Invert Enable\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum CTSINV_A {
92    #[doc = "0: The CTS pin is active low"]
93    DISABLE = 0,
94    #[doc = "1: The CTS pin is active high"]
95    ENABLE = 1,
96}
97impl From<CTSINV_A> for bool {
98    #[inline(always)]
99    fn from(variant: CTSINV_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl CTSINV_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> CTSINV_A {
107        match self.bits {
108            false => CTSINV_A::DISABLE,
109            true => CTSINV_A::ENABLE,
110        }
111    }
112    #[doc = "Checks if the value of the field is `DISABLE`"]
113    #[inline(always)]
114    pub fn is_disable(&self) -> bool {
115        *self == CTSINV_A::DISABLE
116    }
117    #[doc = "Checks if the value of the field is `ENABLE`"]
118    #[inline(always)]
119    pub fn is_enable(&self) -> bool {
120        *self == CTSINV_A::ENABLE
121    }
122}
123#[doc = "Field `CTSINV` writer - Clear-to-send Invert Enable"]
124pub type CTSINV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG1_SPEC, CTSINV_A, O>;
125impl<'a, const O: u8> CTSINV_W<'a, O> {
126    #[doc = "The CTS pin is active low"]
127    #[inline(always)]
128    pub fn disable(self) -> &'a mut W {
129        self.variant(CTSINV_A::DISABLE)
130    }
131    #[doc = "The CTS pin is active high"]
132    #[inline(always)]
133    pub fn enable(self) -> &'a mut W {
134        self.variant(CTSINV_A::ENABLE)
135    }
136}
137#[doc = "Field `CTSEN` reader - Clear-to-send Enable"]
138pub type CTSEN_R = crate::BitReader<CTSEN_A>;
139#[doc = "Clear-to-send Enable\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum CTSEN_A {
142    #[doc = "0: Ignore CTS"]
143    DISABLE = 0,
144    #[doc = "1: Stop transmitting when CTS is inactive"]
145    ENABLE = 1,
146}
147impl From<CTSEN_A> for bool {
148    #[inline(always)]
149    fn from(variant: CTSEN_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl CTSEN_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> CTSEN_A {
157        match self.bits {
158            false => CTSEN_A::DISABLE,
159            true => CTSEN_A::ENABLE,
160        }
161    }
162    #[doc = "Checks if the value of the field is `DISABLE`"]
163    #[inline(always)]
164    pub fn is_disable(&self) -> bool {
165        *self == CTSEN_A::DISABLE
166    }
167    #[doc = "Checks if the value of the field is `ENABLE`"]
168    #[inline(always)]
169    pub fn is_enable(&self) -> bool {
170        *self == CTSEN_A::ENABLE
171    }
172}
173#[doc = "Field `CTSEN` writer - Clear-to-send Enable"]
174pub type CTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG1_SPEC, CTSEN_A, O>;
175impl<'a, const O: u8> CTSEN_W<'a, O> {
176    #[doc = "Ignore CTS"]
177    #[inline(always)]
178    pub fn disable(self) -> &'a mut W {
179        self.variant(CTSEN_A::DISABLE)
180    }
181    #[doc = "Stop transmitting when CTS is inactive"]
182    #[inline(always)]
183    pub fn enable(self) -> &'a mut W {
184        self.variant(CTSEN_A::ENABLE)
185    }
186}
187#[doc = "Field `RTSINV` reader - Request-to-send Invert Enable"]
188pub type RTSINV_R = crate::BitReader<RTSINV_A>;
189#[doc = "Request-to-send Invert Enable\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum RTSINV_A {
192    #[doc = "0: The RTS pin is active low"]
193    DISABLE = 0,
194    #[doc = "1: The RTS pin is active high"]
195    ENABLE = 1,
196}
197impl From<RTSINV_A> for bool {
198    #[inline(always)]
199    fn from(variant: RTSINV_A) -> Self {
200        variant as u8 != 0
201    }
202}
203impl RTSINV_R {
204    #[doc = "Get enumerated values variant"]
205    #[inline(always)]
206    pub fn variant(&self) -> RTSINV_A {
207        match self.bits {
208            false => RTSINV_A::DISABLE,
209            true => RTSINV_A::ENABLE,
210        }
211    }
212    #[doc = "Checks if the value of the field is `DISABLE`"]
213    #[inline(always)]
214    pub fn is_disable(&self) -> bool {
215        *self == RTSINV_A::DISABLE
216    }
217    #[doc = "Checks if the value of the field is `ENABLE`"]
218    #[inline(always)]
219    pub fn is_enable(&self) -> bool {
220        *self == RTSINV_A::ENABLE
221    }
222}
223#[doc = "Field `RTSINV` writer - Request-to-send Invert Enable"]
224pub type RTSINV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG1_SPEC, RTSINV_A, O>;
225impl<'a, const O: u8> RTSINV_W<'a, O> {
226    #[doc = "The RTS pin is active low"]
227    #[inline(always)]
228    pub fn disable(self) -> &'a mut W {
229        self.variant(RTSINV_A::DISABLE)
230    }
231    #[doc = "The RTS pin is active high"]
232    #[inline(always)]
233    pub fn enable(self) -> &'a mut W {
234        self.variant(RTSINV_A::ENABLE)
235    }
236}
237#[doc = "Field `TXDMAWU` reader - Transmitter DMA Wakeup"]
238pub type TXDMAWU_R = crate::BitReader<bool>;
239#[doc = "Field `TXDMAWU` writer - Transmitter DMA Wakeup"]
240pub type TXDMAWU_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG1_SPEC, bool, O>;
241#[doc = "Field `RXDMAWU` reader - Receiver DMA Wakeup"]
242pub type RXDMAWU_R = crate::BitReader<bool>;
243#[doc = "Field `RXDMAWU` writer - Receiver DMA Wakeup"]
244pub type RXDMAWU_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG1_SPEC, bool, O>;
245#[doc = "Field `SFUBRX` reader - Start Frame Unblock Receiver"]
246pub type SFUBRX_R = crate::BitReader<bool>;
247#[doc = "Field `SFUBRX` writer - Start Frame Unblock Receiver"]
248pub type SFUBRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG1_SPEC, bool, O>;
249#[doc = "Field `RXPRSEN` reader - PRS RX Enable"]
250pub type RXPRSEN_R = crate::BitReader<bool>;
251#[doc = "Field `RXPRSEN` writer - PRS RX Enable"]
252pub type RXPRSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG1_SPEC, bool, O>;
253#[doc = "Field `TXFIW` reader - TX FIFO Interrupt Watermark"]
254pub type TXFIW_R = crate::FieldReader<u8, TXFIW_A>;
255#[doc = "TX FIFO Interrupt Watermark\n\nValue on reset: 0"]
256#[derive(Clone, Copy, Debug, PartialEq, Eq)]
257#[repr(u8)]
258pub enum TXFIW_A {
259    #[doc = "0: TXFL status flag and IF are set when the TX FIFO has space for at least one more frame."]
260    ONEFRAME = 0,
261    #[doc = "1: TXFL status flag and IF are set when the TX FIFO has space for at least two more frames."]
262    TWOFRAMES = 1,
263    #[doc = "2: TXFL status flag and IF are set when the TX FIFO has space for at least three more frames."]
264    THREEFRAMES = 2,
265    #[doc = "3: TXFL status flag and IF are set when the TX FIFO has space for at least four more frames."]
266    FOURFRAMES = 3,
267}
268impl From<TXFIW_A> for u8 {
269    #[inline(always)]
270    fn from(variant: TXFIW_A) -> Self {
271        variant as _
272    }
273}
274impl TXFIW_R {
275    #[doc = "Get enumerated values variant"]
276    #[inline(always)]
277    pub fn variant(&self) -> TXFIW_A {
278        match self.bits {
279            0 => TXFIW_A::ONEFRAME,
280            1 => TXFIW_A::TWOFRAMES,
281            2 => TXFIW_A::THREEFRAMES,
282            3 => TXFIW_A::FOURFRAMES,
283            _ => unreachable!(),
284        }
285    }
286    #[doc = "Checks if the value of the field is `ONEFRAME`"]
287    #[inline(always)]
288    pub fn is_oneframe(&self) -> bool {
289        *self == TXFIW_A::ONEFRAME
290    }
291    #[doc = "Checks if the value of the field is `TWOFRAMES`"]
292    #[inline(always)]
293    pub fn is_twoframes(&self) -> bool {
294        *self == TXFIW_A::TWOFRAMES
295    }
296    #[doc = "Checks if the value of the field is `THREEFRAMES`"]
297    #[inline(always)]
298    pub fn is_threeframes(&self) -> bool {
299        *self == TXFIW_A::THREEFRAMES
300    }
301    #[doc = "Checks if the value of the field is `FOURFRAMES`"]
302    #[inline(always)]
303    pub fn is_fourframes(&self) -> bool {
304        *self == TXFIW_A::FOURFRAMES
305    }
306}
307#[doc = "Field `TXFIW` writer - TX FIFO Interrupt Watermark"]
308pub type TXFIW_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CFG1_SPEC, u8, TXFIW_A, 2, O>;
309impl<'a, const O: u8> TXFIW_W<'a, O> {
310    #[doc = "TXFL status flag and IF are set when the TX FIFO has space for at least one more frame."]
311    #[inline(always)]
312    pub fn oneframe(self) -> &'a mut W {
313        self.variant(TXFIW_A::ONEFRAME)
314    }
315    #[doc = "TXFL status flag and IF are set when the TX FIFO has space for at least two more frames."]
316    #[inline(always)]
317    pub fn twoframes(self) -> &'a mut W {
318        self.variant(TXFIW_A::TWOFRAMES)
319    }
320    #[doc = "TXFL status flag and IF are set when the TX FIFO has space for at least three more frames."]
321    #[inline(always)]
322    pub fn threeframes(self) -> &'a mut W {
323        self.variant(TXFIW_A::THREEFRAMES)
324    }
325    #[doc = "TXFL status flag and IF are set when the TX FIFO has space for at least four more frames."]
326    #[inline(always)]
327    pub fn fourframes(self) -> &'a mut W {
328        self.variant(TXFIW_A::FOURFRAMES)
329    }
330}
331#[doc = "Field `RXFIW` reader - RX FIFO Interrupt Watermark"]
332pub type RXFIW_R = crate::FieldReader<u8, RXFIW_A>;
333#[doc = "RX FIFO Interrupt Watermark\n\nValue on reset: 0"]
334#[derive(Clone, Copy, Debug, PartialEq, Eq)]
335#[repr(u8)]
336pub enum RXFIW_A {
337    #[doc = "0: RXFL status flag and IF are set when the RX FIFO has at least one frame in it."]
338    ONEFRAME = 0,
339    #[doc = "1: RXFL status flag and IF are set when the RX FIFO has at least two frames in it."]
340    TWOFRAMES = 1,
341    #[doc = "2: RXFL status flag and IF are set when the RX FIFO has at least three frames in it."]
342    THREEFRAMES = 2,
343    #[doc = "3: RXFL status flag and IF are set when the RX FIFO has four frames in it."]
344    FOURFRAMES = 3,
345}
346impl From<RXFIW_A> for u8 {
347    #[inline(always)]
348    fn from(variant: RXFIW_A) -> Self {
349        variant as _
350    }
351}
352impl RXFIW_R {
353    #[doc = "Get enumerated values variant"]
354    #[inline(always)]
355    pub fn variant(&self) -> RXFIW_A {
356        match self.bits {
357            0 => RXFIW_A::ONEFRAME,
358            1 => RXFIW_A::TWOFRAMES,
359            2 => RXFIW_A::THREEFRAMES,
360            3 => RXFIW_A::FOURFRAMES,
361            _ => unreachable!(),
362        }
363    }
364    #[doc = "Checks if the value of the field is `ONEFRAME`"]
365    #[inline(always)]
366    pub fn is_oneframe(&self) -> bool {
367        *self == RXFIW_A::ONEFRAME
368    }
369    #[doc = "Checks if the value of the field is `TWOFRAMES`"]
370    #[inline(always)]
371    pub fn is_twoframes(&self) -> bool {
372        *self == RXFIW_A::TWOFRAMES
373    }
374    #[doc = "Checks if the value of the field is `THREEFRAMES`"]
375    #[inline(always)]
376    pub fn is_threeframes(&self) -> bool {
377        *self == RXFIW_A::THREEFRAMES
378    }
379    #[doc = "Checks if the value of the field is `FOURFRAMES`"]
380    #[inline(always)]
381    pub fn is_fourframes(&self) -> bool {
382        *self == RXFIW_A::FOURFRAMES
383    }
384}
385#[doc = "Field `RXFIW` writer - RX FIFO Interrupt Watermark"]
386pub type RXFIW_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CFG1_SPEC, u8, RXFIW_A, 2, O>;
387impl<'a, const O: u8> RXFIW_W<'a, O> {
388    #[doc = "RXFL status flag and IF are set when the RX FIFO has at least one frame in it."]
389    #[inline(always)]
390    pub fn oneframe(self) -> &'a mut W {
391        self.variant(RXFIW_A::ONEFRAME)
392    }
393    #[doc = "RXFL status flag and IF are set when the RX FIFO has at least two frames in it."]
394    #[inline(always)]
395    pub fn twoframes(self) -> &'a mut W {
396        self.variant(RXFIW_A::TWOFRAMES)
397    }
398    #[doc = "RXFL status flag and IF are set when the RX FIFO has at least three frames in it."]
399    #[inline(always)]
400    pub fn threeframes(self) -> &'a mut W {
401        self.variant(RXFIW_A::THREEFRAMES)
402    }
403    #[doc = "RXFL status flag and IF are set when the RX FIFO has four frames in it."]
404    #[inline(always)]
405    pub fn fourframes(self) -> &'a mut W {
406        self.variant(RXFIW_A::FOURFRAMES)
407    }
408}
409#[doc = "Field `RTSRXFW` reader - Request-to-send RX FIFO Watermark"]
410pub type RTSRXFW_R = crate::FieldReader<u8, RTSRXFW_A>;
411#[doc = "Request-to-send RX FIFO Watermark\n\nValue on reset: 0"]
412#[derive(Clone, Copy, Debug, PartialEq, Eq)]
413#[repr(u8)]
414pub enum RTSRXFW_A {
415    #[doc = "0: RTS is set if there is space for at least one more frame in the RX FIFO."]
416    ONEFRAME = 0,
417    #[doc = "1: RTS is set if there is space for at least two more frames in the RX FIFO."]
418    TWOFRAMES = 1,
419    #[doc = "2: RTS is set if there is space for at least three more frames in the RX FIFO."]
420    THREEFRAMES = 2,
421    #[doc = "3: RTS is set if there is space for four more frames in the RX FIFO."]
422    FOURFRAMES = 3,
423}
424impl From<RTSRXFW_A> for u8 {
425    #[inline(always)]
426    fn from(variant: RTSRXFW_A) -> Self {
427        variant as _
428    }
429}
430impl RTSRXFW_R {
431    #[doc = "Get enumerated values variant"]
432    #[inline(always)]
433    pub fn variant(&self) -> RTSRXFW_A {
434        match self.bits {
435            0 => RTSRXFW_A::ONEFRAME,
436            1 => RTSRXFW_A::TWOFRAMES,
437            2 => RTSRXFW_A::THREEFRAMES,
438            3 => RTSRXFW_A::FOURFRAMES,
439            _ => unreachable!(),
440        }
441    }
442    #[doc = "Checks if the value of the field is `ONEFRAME`"]
443    #[inline(always)]
444    pub fn is_oneframe(&self) -> bool {
445        *self == RTSRXFW_A::ONEFRAME
446    }
447    #[doc = "Checks if the value of the field is `TWOFRAMES`"]
448    #[inline(always)]
449    pub fn is_twoframes(&self) -> bool {
450        *self == RTSRXFW_A::TWOFRAMES
451    }
452    #[doc = "Checks if the value of the field is `THREEFRAMES`"]
453    #[inline(always)]
454    pub fn is_threeframes(&self) -> bool {
455        *self == RTSRXFW_A::THREEFRAMES
456    }
457    #[doc = "Checks if the value of the field is `FOURFRAMES`"]
458    #[inline(always)]
459    pub fn is_fourframes(&self) -> bool {
460        *self == RTSRXFW_A::FOURFRAMES
461    }
462}
463#[doc = "Field `RTSRXFW` writer - Request-to-send RX FIFO Watermark"]
464pub type RTSRXFW_W<'a, const O: u8> =
465    crate::FieldWriterSafe<'a, u32, CFG1_SPEC, u8, RTSRXFW_A, 2, O>;
466impl<'a, const O: u8> RTSRXFW_W<'a, O> {
467    #[doc = "RTS is set if there is space for at least one more frame in the RX FIFO."]
468    #[inline(always)]
469    pub fn oneframe(self) -> &'a mut W {
470        self.variant(RTSRXFW_A::ONEFRAME)
471    }
472    #[doc = "RTS is set if there is space for at least two more frames in the RX FIFO."]
473    #[inline(always)]
474    pub fn twoframes(self) -> &'a mut W {
475        self.variant(RTSRXFW_A::TWOFRAMES)
476    }
477    #[doc = "RTS is set if there is space for at least three more frames in the RX FIFO."]
478    #[inline(always)]
479    pub fn threeframes(self) -> &'a mut W {
480        self.variant(RTSRXFW_A::THREEFRAMES)
481    }
482    #[doc = "RTS is set if there is space for four more frames in the RX FIFO."]
483    #[inline(always)]
484    pub fn fourframes(self) -> &'a mut W {
485        self.variant(RTSRXFW_A::FOURFRAMES)
486    }
487}
488impl R {
489    #[doc = "Bit 0 - Debug halt"]
490    #[inline(always)]
491    pub fn dbghalt(&self) -> DBGHALT_R {
492        DBGHALT_R::new((self.bits & 1) != 0)
493    }
494    #[doc = "Bit 1 - Clear-to-send Invert Enable"]
495    #[inline(always)]
496    pub fn ctsinv(&self) -> CTSINV_R {
497        CTSINV_R::new(((self.bits >> 1) & 1) != 0)
498    }
499    #[doc = "Bit 2 - Clear-to-send Enable"]
500    #[inline(always)]
501    pub fn ctsen(&self) -> CTSEN_R {
502        CTSEN_R::new(((self.bits >> 2) & 1) != 0)
503    }
504    #[doc = "Bit 3 - Request-to-send Invert Enable"]
505    #[inline(always)]
506    pub fn rtsinv(&self) -> RTSINV_R {
507        RTSINV_R::new(((self.bits >> 3) & 1) != 0)
508    }
509    #[doc = "Bit 9 - Transmitter DMA Wakeup"]
510    #[inline(always)]
511    pub fn txdmawu(&self) -> TXDMAWU_R {
512        TXDMAWU_R::new(((self.bits >> 9) & 1) != 0)
513    }
514    #[doc = "Bit 10 - Receiver DMA Wakeup"]
515    #[inline(always)]
516    pub fn rxdmawu(&self) -> RXDMAWU_R {
517        RXDMAWU_R::new(((self.bits >> 10) & 1) != 0)
518    }
519    #[doc = "Bit 11 - Start Frame Unblock Receiver"]
520    #[inline(always)]
521    pub fn sfubrx(&self) -> SFUBRX_R {
522        SFUBRX_R::new(((self.bits >> 11) & 1) != 0)
523    }
524    #[doc = "Bit 15 - PRS RX Enable"]
525    #[inline(always)]
526    pub fn rxprsen(&self) -> RXPRSEN_R {
527        RXPRSEN_R::new(((self.bits >> 15) & 1) != 0)
528    }
529    #[doc = "Bits 16:17 - TX FIFO Interrupt Watermark"]
530    #[inline(always)]
531    pub fn txfiw(&self) -> TXFIW_R {
532        TXFIW_R::new(((self.bits >> 16) & 3) as u8)
533    }
534    #[doc = "Bits 19:20 - RX FIFO Interrupt Watermark"]
535    #[inline(always)]
536    pub fn rxfiw(&self) -> RXFIW_R {
537        RXFIW_R::new(((self.bits >> 19) & 3) as u8)
538    }
539    #[doc = "Bits 22:23 - Request-to-send RX FIFO Watermark"]
540    #[inline(always)]
541    pub fn rtsrxfw(&self) -> RTSRXFW_R {
542        RTSRXFW_R::new(((self.bits >> 22) & 3) as u8)
543    }
544}
545impl W {
546    #[doc = "Bit 0 - Debug halt"]
547    #[inline(always)]
548    #[must_use]
549    pub fn dbghalt(&mut self) -> DBGHALT_W<0> {
550        DBGHALT_W::new(self)
551    }
552    #[doc = "Bit 1 - Clear-to-send Invert Enable"]
553    #[inline(always)]
554    #[must_use]
555    pub fn ctsinv(&mut self) -> CTSINV_W<1> {
556        CTSINV_W::new(self)
557    }
558    #[doc = "Bit 2 - Clear-to-send Enable"]
559    #[inline(always)]
560    #[must_use]
561    pub fn ctsen(&mut self) -> CTSEN_W<2> {
562        CTSEN_W::new(self)
563    }
564    #[doc = "Bit 3 - Request-to-send Invert Enable"]
565    #[inline(always)]
566    #[must_use]
567    pub fn rtsinv(&mut self) -> RTSINV_W<3> {
568        RTSINV_W::new(self)
569    }
570    #[doc = "Bit 9 - Transmitter DMA Wakeup"]
571    #[inline(always)]
572    #[must_use]
573    pub fn txdmawu(&mut self) -> TXDMAWU_W<9> {
574        TXDMAWU_W::new(self)
575    }
576    #[doc = "Bit 10 - Receiver DMA Wakeup"]
577    #[inline(always)]
578    #[must_use]
579    pub fn rxdmawu(&mut self) -> RXDMAWU_W<10> {
580        RXDMAWU_W::new(self)
581    }
582    #[doc = "Bit 11 - Start Frame Unblock Receiver"]
583    #[inline(always)]
584    #[must_use]
585    pub fn sfubrx(&mut self) -> SFUBRX_W<11> {
586        SFUBRX_W::new(self)
587    }
588    #[doc = "Bit 15 - PRS RX Enable"]
589    #[inline(always)]
590    #[must_use]
591    pub fn rxprsen(&mut self) -> RXPRSEN_W<15> {
592        RXPRSEN_W::new(self)
593    }
594    #[doc = "Bits 16:17 - TX FIFO Interrupt Watermark"]
595    #[inline(always)]
596    #[must_use]
597    pub fn txfiw(&mut self) -> TXFIW_W<16> {
598        TXFIW_W::new(self)
599    }
600    #[doc = "Bits 19:20 - RX FIFO Interrupt Watermark"]
601    #[inline(always)]
602    #[must_use]
603    pub fn rxfiw(&mut self) -> RXFIW_W<19> {
604        RXFIW_W::new(self)
605    }
606    #[doc = "Bits 22:23 - Request-to-send RX FIFO Watermark"]
607    #[inline(always)]
608    #[must_use]
609    pub fn rtsrxfw(&mut self) -> RTSRXFW_W<22> {
610        RTSRXFW_W::new(self)
611    }
612    #[doc = "Writes raw bits to the register."]
613    #[inline(always)]
614    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
615        self.0.bits(bits);
616        self
617    }
618}
619#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg1](index.html) module"]
620pub struct CFG1_SPEC;
621impl crate::RegisterSpec for CFG1_SPEC {
622    type Ux = u32;
623}
624#[doc = "`read()` method returns [cfg1::R](R) reader structure"]
625impl crate::Readable for CFG1_SPEC {
626    type Reader = R;
627}
628#[doc = "`write(|w| ..)` method takes [cfg1::W](W) writer structure"]
629impl crate::Writable for CFG1_SPEC {
630    type Writer = W;
631    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
632    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
633}
634#[doc = "`reset()` method sets CFG1 to value 0"]
635impl crate::Resettable for CFG1_SPEC {
636    const RESET_VALUE: Self::Ux = 0;
637}
efm32pg22_pac/efm32pg22c200/euart0_ns/cfg1.rs

efm32pg22_pac/efm32pg22c200/euart0_ns/
cfg1.rs
