efm32pg22_pac/efm32pg22c200/dpll0_ns/
cfg.rs

1#[doc = "Register `CFG` reader"]
2pub struct R(crate::R<CFG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CFG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CFG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CFG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CFG` writer"]
17pub struct W(crate::W<CFG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CFG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CFG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CFG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MODE` reader - Operating Mode Control"]
38pub type MODE_R = crate::BitReader<MODE_A>;
39#[doc = "Operating Mode Control\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum MODE_A {
42    #[doc = "0: Frequency Lock Mode"]
43    FLL = 0,
44    #[doc = "1: Phase Lock Mode"]
45    PLL = 1,
46}
47impl From<MODE_A> for bool {
48    #[inline(always)]
49    fn from(variant: MODE_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl MODE_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> MODE_A {
57        match self.bits {
58            false => MODE_A::FLL,
59            true => MODE_A::PLL,
60        }
61    }
62    #[doc = "Checks if the value of the field is `FLL`"]
63    #[inline(always)]
64    pub fn is_fll(&self) -> bool {
65        *self == MODE_A::FLL
66    }
67    #[doc = "Checks if the value of the field is `PLL`"]
68    #[inline(always)]
69    pub fn is_pll(&self) -> bool {
70        *self == MODE_A::PLL
71    }
72}
73#[doc = "Field `MODE` writer - Operating Mode Control"]
74pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, MODE_A, O>;
75impl<'a, const O: u8> MODE_W<'a, O> {
76    #[doc = "Frequency Lock Mode"]
77    #[inline(always)]
78    pub fn fll(self) -> &'a mut W {
79        self.variant(MODE_A::FLL)
80    }
81    #[doc = "Phase Lock Mode"]
82    #[inline(always)]
83    pub fn pll(self) -> &'a mut W {
84        self.variant(MODE_A::PLL)
85    }
86}
87#[doc = "Field `EDGESEL` reader - Reference Edge Select"]
88pub type EDGESEL_R = crate::BitReader<bool>;
89#[doc = "Field `EDGESEL` writer - Reference Edge Select"]
90pub type EDGESEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, bool, O>;
91#[doc = "Field `AUTORECOVER` reader - Automatic Recovery Control"]
92pub type AUTORECOVER_R = crate::BitReader<bool>;
93#[doc = "Field `AUTORECOVER` writer - Automatic Recovery Control"]
94pub type AUTORECOVER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, bool, O>;
95#[doc = "Field `DITHEN` reader - Dither Enable Control"]
96pub type DITHEN_R = crate::BitReader<bool>;
97#[doc = "Field `DITHEN` writer - Dither Enable Control"]
98pub type DITHEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, bool, O>;
99impl R {
100    #[doc = "Bit 0 - Operating Mode Control"]
101    #[inline(always)]
102    pub fn mode(&self) -> MODE_R {
103        MODE_R::new((self.bits & 1) != 0)
104    }
105    #[doc = "Bit 1 - Reference Edge Select"]
106    #[inline(always)]
107    pub fn edgesel(&self) -> EDGESEL_R {
108        EDGESEL_R::new(((self.bits >> 1) & 1) != 0)
109    }
110    #[doc = "Bit 2 - Automatic Recovery Control"]
111    #[inline(always)]
112    pub fn autorecover(&self) -> AUTORECOVER_R {
113        AUTORECOVER_R::new(((self.bits >> 2) & 1) != 0)
114    }
115    #[doc = "Bit 6 - Dither Enable Control"]
116    #[inline(always)]
117    pub fn dithen(&self) -> DITHEN_R {
118        DITHEN_R::new(((self.bits >> 6) & 1) != 0)
119    }
120}
121impl W {
122    #[doc = "Bit 0 - Operating Mode Control"]
123    #[inline(always)]
124    #[must_use]
125    pub fn mode(&mut self) -> MODE_W<0> {
126        MODE_W::new(self)
127    }
128    #[doc = "Bit 1 - Reference Edge Select"]
129    #[inline(always)]
130    #[must_use]
131    pub fn edgesel(&mut self) -> EDGESEL_W<1> {
132        EDGESEL_W::new(self)
133    }
134    #[doc = "Bit 2 - Automatic Recovery Control"]
135    #[inline(always)]
136    #[must_use]
137    pub fn autorecover(&mut self) -> AUTORECOVER_W<2> {
138        AUTORECOVER_W::new(self)
139    }
140    #[doc = "Bit 6 - Dither Enable Control"]
141    #[inline(always)]
142    #[must_use]
143    pub fn dithen(&mut self) -> DITHEN_W<6> {
144        DITHEN_W::new(self)
145    }
146    #[doc = "Writes raw bits to the register."]
147    #[inline(always)]
148    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
149        self.0.bits(bits);
150        self
151    }
152}
153#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
154pub struct CFG_SPEC;
155impl crate::RegisterSpec for CFG_SPEC {
156    type Ux = u32;
157}
158#[doc = "`read()` method returns [cfg::R](R) reader structure"]
159impl crate::Readable for CFG_SPEC {
160    type Reader = R;
161}
162#[doc = "`write(|w| ..)` method takes [cfg::W](W) writer structure"]
163impl crate::Writable for CFG_SPEC {
164    type Writer = W;
165    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
166    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
167}
168#[doc = "`reset()` method sets CFG to value 0"]
169impl crate::Resettable for CFG_SPEC {
170    const RESET_VALUE: Self::Ux = 0;
171}
efm32pg22_pac/efm32pg22c200/dpll0_ns/cfg.rs

efm32pg22_pac/efm32pg22c200/dpll0_ns/
cfg.rs
