efm32pg22_pac/efm32pg22c200/cryptoacc_s/
incl_ips_hw_cfg.rs

1#[doc = "Register `INCL_IPS_HW_CFG` reader"]
2pub struct R(crate::R<INCL_IPS_HW_CFG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INCL_IPS_HW_CFG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INCL_IPS_HW_CFG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INCL_IPS_HW_CFG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `g_IncludeAES` reader - Generic g_IncludeAES value"]
17pub type G_INCLUDE_AES_R = crate::BitReader<bool>;
18#[doc = "Field `g_IncludeAESGCM` reader - Generic g_IncludeAESGCM value"]
19pub type G_INCLUDE_AESGCM_R = crate::BitReader<bool>;
20#[doc = "Field `g_IncludeAESXTS` reader - Generic g_IncludeAESXTS value"]
21pub type G_INCLUDE_AESXTS_R = crate::BitReader<bool>;
22#[doc = "Field `g_IncludeDES` reader - Generic g_IncludeDES value"]
23pub type G_INCLUDE_DES_R = crate::BitReader<bool>;
24#[doc = "Field `g_IncludeHASH` reader - Generic g_IncludeHASH value"]
25pub type G_INCLUDE_HASH_R = crate::BitReader<bool>;
26#[doc = "Field `g_IncludeChachaPoly` reader - Generic g_IncludeChachaPoly value"]
27pub type G_INCLUDE_CHACHA_POLY_R = crate::BitReader<bool>;
28#[doc = "Field `g_IncludeSHA3` reader - Generic g_IncludeSHA3 value"]
29pub type G_INCLUDE_SHA3_R = crate::BitReader<bool>;
30#[doc = "Field `g_IncludeZUC` reader - Generic g_IncludeZUC value"]
31pub type G_INCLUDE_ZUC_R = crate::BitReader<bool>;
32#[doc = "Field `g_IncludeSM4` reader - Generic g_IncludeSM4 value"]
33pub type G_INCLUDE_SM4_R = crate::BitReader<bool>;
34#[doc = "Field `g_IncludePKE` reader - Generic g_IncludePKE value"]
35pub type G_INCLUDE_PKE_R = crate::BitReader<bool>;
36#[doc = "Field `g_IncludeNDRNG` reader - Generic g_IncludeNDRNG value"]
37pub type G_INCLUDE_NDRNG_R = crate::BitReader<bool>;
38impl R {
39    #[doc = "Bit 0 - Generic g_IncludeAES value"]
40    #[inline(always)]
41    pub fn g_include_aes(&self) -> G_INCLUDE_AES_R {
42        G_INCLUDE_AES_R::new((self.bits & 1) != 0)
43    }
44    #[doc = "Bit 1 - Generic g_IncludeAESGCM value"]
45    #[inline(always)]
46    pub fn g_include_aesgcm(&self) -> G_INCLUDE_AESGCM_R {
47        G_INCLUDE_AESGCM_R::new(((self.bits >> 1) & 1) != 0)
48    }
49    #[doc = "Bit 2 - Generic g_IncludeAESXTS value"]
50    #[inline(always)]
51    pub fn g_include_aesxts(&self) -> G_INCLUDE_AESXTS_R {
52        G_INCLUDE_AESXTS_R::new(((self.bits >> 2) & 1) != 0)
53    }
54    #[doc = "Bit 3 - Generic g_IncludeDES value"]
55    #[inline(always)]
56    pub fn g_include_des(&self) -> G_INCLUDE_DES_R {
57        G_INCLUDE_DES_R::new(((self.bits >> 3) & 1) != 0)
58    }
59    #[doc = "Bit 4 - Generic g_IncludeHASH value"]
60    #[inline(always)]
61    pub fn g_include_hash(&self) -> G_INCLUDE_HASH_R {
62        G_INCLUDE_HASH_R::new(((self.bits >> 4) & 1) != 0)
63    }
64    #[doc = "Bit 5 - Generic g_IncludeChachaPoly value"]
65    #[inline(always)]
66    pub fn g_include_chacha_poly(&self) -> G_INCLUDE_CHACHA_POLY_R {
67        G_INCLUDE_CHACHA_POLY_R::new(((self.bits >> 5) & 1) != 0)
68    }
69    #[doc = "Bit 6 - Generic g_IncludeSHA3 value"]
70    #[inline(always)]
71    pub fn g_include_sha3(&self) -> G_INCLUDE_SHA3_R {
72        G_INCLUDE_SHA3_R::new(((self.bits >> 6) & 1) != 0)
73    }
74    #[doc = "Bit 7 - Generic g_IncludeZUC value"]
75    #[inline(always)]
76    pub fn g_include_zuc(&self) -> G_INCLUDE_ZUC_R {
77        G_INCLUDE_ZUC_R::new(((self.bits >> 7) & 1) != 0)
78    }
79    #[doc = "Bit 8 - Generic g_IncludeSM4 value"]
80    #[inline(always)]
81    pub fn g_include_sm4(&self) -> G_INCLUDE_SM4_R {
82        G_INCLUDE_SM4_R::new(((self.bits >> 8) & 1) != 0)
83    }
84    #[doc = "Bit 9 - Generic g_IncludePKE value"]
85    #[inline(always)]
86    pub fn g_include_pke(&self) -> G_INCLUDE_PKE_R {
87        G_INCLUDE_PKE_R::new(((self.bits >> 9) & 1) != 0)
88    }
89    #[doc = "Bit 10 - Generic g_IncludeNDRNG value"]
90    #[inline(always)]
91    pub fn g_include_ndrng(&self) -> G_INCLUDE_NDRNG_R {
92        G_INCLUDE_NDRNG_R::new(((self.bits >> 10) & 1) != 0)
93    }
94}
95#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [incl_ips_hw_cfg](index.html) module"]
96pub struct INCL_IPS_HW_CFG_SPEC;
97impl crate::RegisterSpec for INCL_IPS_HW_CFG_SPEC {
98    type Ux = u32;
99}
100#[doc = "`read()` method returns [incl_ips_hw_cfg::R](R) reader structure"]
101impl crate::Readable for INCL_IPS_HW_CFG_SPEC {
102    type Reader = R;
103}
104#[doc = "`reset()` method sets INCL_IPS_HW_CFG to value 0x0611"]
105impl crate::Resettable for INCL_IPS_HW_CFG_SPEC {
106    const RESET_VALUE: Self::Ux = 0x0611;
107}
efm32pg22_pac/efm32pg22c200/cryptoacc_s/incl_ips_hw_cfg.rs

efm32pg22_pac/efm32pg22c200/cryptoacc_s/
incl_ips_hw_cfg.rs
