efm32pg22_pac/efm32pg22c200/cmu_s/
sysclkctrl.rs

1#[doc = "Register `SYSCLKCTRL` reader"]
2pub struct R(crate::R<SYSCLKCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SYSCLKCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SYSCLKCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SYSCLKCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SYSCLKCTRL` writer"]
17pub struct W(crate::W<SYSCLKCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SYSCLKCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SYSCLKCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SYSCLKCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CLKSEL` reader - Clock Select"]
38pub type CLKSEL_R = crate::FieldReader<u8, CLKSEL_A>;
39#[doc = "Clock Select\n\nValue on reset: 1"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CLKSEL_A {
43    #[doc = "1: FSRCO is clocking SYSCLK"]
44    FSRCO = 1,
45    #[doc = "2: HFRCODPLL is clocking SYSCLK"]
46    HFRCODPLL = 2,
47    #[doc = "3: HFXO is clocking SYSCLK"]
48    HFXO = 3,
49    #[doc = "4: CLKIN0 is clocking SYSCLK"]
50    CLKIN0 = 4,
51}
52impl From<CLKSEL_A> for u8 {
53    #[inline(always)]
54    fn from(variant: CLKSEL_A) -> Self {
55        variant as _
56    }
57}
58impl CLKSEL_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> Option<CLKSEL_A> {
62        match self.bits {
63            1 => Some(CLKSEL_A::FSRCO),
64            2 => Some(CLKSEL_A::HFRCODPLL),
65            3 => Some(CLKSEL_A::HFXO),
66            4 => Some(CLKSEL_A::CLKIN0),
67            _ => None,
68        }
69    }
70    #[doc = "Checks if the value of the field is `FSRCO`"]
71    #[inline(always)]
72    pub fn is_fsrco(&self) -> bool {
73        *self == CLKSEL_A::FSRCO
74    }
75    #[doc = "Checks if the value of the field is `HFRCODPLL`"]
76    #[inline(always)]
77    pub fn is_hfrcodpll(&self) -> bool {
78        *self == CLKSEL_A::HFRCODPLL
79    }
80    #[doc = "Checks if the value of the field is `HFXO`"]
81    #[inline(always)]
82    pub fn is_hfxo(&self) -> bool {
83        *self == CLKSEL_A::HFXO
84    }
85    #[doc = "Checks if the value of the field is `CLKIN0`"]
86    #[inline(always)]
87    pub fn is_clkin0(&self) -> bool {
88        *self == CLKSEL_A::CLKIN0
89    }
90}
91#[doc = "Field `CLKSEL` writer - Clock Select"]
92pub type CLKSEL_W<'a, const O: u8> =
93    crate::FieldWriter<'a, u32, SYSCLKCTRL_SPEC, u8, CLKSEL_A, 3, O>;
94impl<'a, const O: u8> CLKSEL_W<'a, O> {
95    #[doc = "FSRCO is clocking SYSCLK"]
96    #[inline(always)]
97    pub fn fsrco(self) -> &'a mut W {
98        self.variant(CLKSEL_A::FSRCO)
99    }
100    #[doc = "HFRCODPLL is clocking SYSCLK"]
101    #[inline(always)]
102    pub fn hfrcodpll(self) -> &'a mut W {
103        self.variant(CLKSEL_A::HFRCODPLL)
104    }
105    #[doc = "HFXO is clocking SYSCLK"]
106    #[inline(always)]
107    pub fn hfxo(self) -> &'a mut W {
108        self.variant(CLKSEL_A::HFXO)
109    }
110    #[doc = "CLKIN0 is clocking SYSCLK"]
111    #[inline(always)]
112    pub fn clkin0(self) -> &'a mut W {
113        self.variant(CLKSEL_A::CLKIN0)
114    }
115}
116#[doc = "Field `PCLKPRESC` reader - PCLK Prescaler"]
117pub type PCLKPRESC_R = crate::BitReader<PCLKPRESC_A>;
118#[doc = "PCLK Prescaler\n\nValue on reset: 0"]
119#[derive(Clone, Copy, Debug, PartialEq, Eq)]
120pub enum PCLKPRESC_A {
121    #[doc = "0: PCLK is HCLK divided by 1"]
122    DIV1 = 0,
123    #[doc = "1: PCLK is HCLK divided by 2"]
124    DIV2 = 1,
125}
126impl From<PCLKPRESC_A> for bool {
127    #[inline(always)]
128    fn from(variant: PCLKPRESC_A) -> Self {
129        variant as u8 != 0
130    }
131}
132impl PCLKPRESC_R {
133    #[doc = "Get enumerated values variant"]
134    #[inline(always)]
135    pub fn variant(&self) -> PCLKPRESC_A {
136        match self.bits {
137            false => PCLKPRESC_A::DIV1,
138            true => PCLKPRESC_A::DIV2,
139        }
140    }
141    #[doc = "Checks if the value of the field is `DIV1`"]
142    #[inline(always)]
143    pub fn is_div1(&self) -> bool {
144        *self == PCLKPRESC_A::DIV1
145    }
146    #[doc = "Checks if the value of the field is `DIV2`"]
147    #[inline(always)]
148    pub fn is_div2(&self) -> bool {
149        *self == PCLKPRESC_A::DIV2
150    }
151}
152#[doc = "Field `PCLKPRESC` writer - PCLK Prescaler"]
153pub type PCLKPRESC_W<'a, const O: u8> = crate::BitWriter<'a, u32, SYSCLKCTRL_SPEC, PCLKPRESC_A, O>;
154impl<'a, const O: u8> PCLKPRESC_W<'a, O> {
155    #[doc = "PCLK is HCLK divided by 1"]
156    #[inline(always)]
157    pub fn div1(self) -> &'a mut W {
158        self.variant(PCLKPRESC_A::DIV1)
159    }
160    #[doc = "PCLK is HCLK divided by 2"]
161    #[inline(always)]
162    pub fn div2(self) -> &'a mut W {
163        self.variant(PCLKPRESC_A::DIV2)
164    }
165}
166#[doc = "Field `HCLKPRESC` reader - HCLK Prescaler"]
167pub type HCLKPRESC_R = crate::FieldReader<u8, HCLKPRESC_A>;
168#[doc = "HCLK Prescaler\n\nValue on reset: 0"]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170#[repr(u8)]
171pub enum HCLKPRESC_A {
172    #[doc = "0: HCLK is SYSCLK divided by 1"]
173    DIV1 = 0,
174    #[doc = "1: HCLK is SYSCLK divided by 2"]
175    DIV2 = 1,
176    #[doc = "3: HCLK is SYSCLK divided by 4"]
177    DIV4 = 3,
178    #[doc = "7: HCLK is SYSCLK divided by 8"]
179    DIV8 = 7,
180    #[doc = "15: HCLK is SYSCLK divided by 16"]
181    DIV16 = 15,
182}
183impl From<HCLKPRESC_A> for u8 {
184    #[inline(always)]
185    fn from(variant: HCLKPRESC_A) -> Self {
186        variant as _
187    }
188}
189impl HCLKPRESC_R {
190    #[doc = "Get enumerated values variant"]
191    #[inline(always)]
192    pub fn variant(&self) -> Option<HCLKPRESC_A> {
193        match self.bits {
194            0 => Some(HCLKPRESC_A::DIV1),
195            1 => Some(HCLKPRESC_A::DIV2),
196            3 => Some(HCLKPRESC_A::DIV4),
197            7 => Some(HCLKPRESC_A::DIV8),
198            15 => Some(HCLKPRESC_A::DIV16),
199            _ => None,
200        }
201    }
202    #[doc = "Checks if the value of the field is `DIV1`"]
203    #[inline(always)]
204    pub fn is_div1(&self) -> bool {
205        *self == HCLKPRESC_A::DIV1
206    }
207    #[doc = "Checks if the value of the field is `DIV2`"]
208    #[inline(always)]
209    pub fn is_div2(&self) -> bool {
210        *self == HCLKPRESC_A::DIV2
211    }
212    #[doc = "Checks if the value of the field is `DIV4`"]
213    #[inline(always)]
214    pub fn is_div4(&self) -> bool {
215        *self == HCLKPRESC_A::DIV4
216    }
217    #[doc = "Checks if the value of the field is `DIV8`"]
218    #[inline(always)]
219    pub fn is_div8(&self) -> bool {
220        *self == HCLKPRESC_A::DIV8
221    }
222    #[doc = "Checks if the value of the field is `DIV16`"]
223    #[inline(always)]
224    pub fn is_div16(&self) -> bool {
225        *self == HCLKPRESC_A::DIV16
226    }
227}
228#[doc = "Field `HCLKPRESC` writer - HCLK Prescaler"]
229pub type HCLKPRESC_W<'a, const O: u8> =
230    crate::FieldWriter<'a, u32, SYSCLKCTRL_SPEC, u8, HCLKPRESC_A, 4, O>;
231impl<'a, const O: u8> HCLKPRESC_W<'a, O> {
232    #[doc = "HCLK is SYSCLK divided by 1"]
233    #[inline(always)]
234    pub fn div1(self) -> &'a mut W {
235        self.variant(HCLKPRESC_A::DIV1)
236    }
237    #[doc = "HCLK is SYSCLK divided by 2"]
238    #[inline(always)]
239    pub fn div2(self) -> &'a mut W {
240        self.variant(HCLKPRESC_A::DIV2)
241    }
242    #[doc = "HCLK is SYSCLK divided by 4"]
243    #[inline(always)]
244    pub fn div4(self) -> &'a mut W {
245        self.variant(HCLKPRESC_A::DIV4)
246    }
247    #[doc = "HCLK is SYSCLK divided by 8"]
248    #[inline(always)]
249    pub fn div8(self) -> &'a mut W {
250        self.variant(HCLKPRESC_A::DIV8)
251    }
252    #[doc = "HCLK is SYSCLK divided by 16"]
253    #[inline(always)]
254    pub fn div16(self) -> &'a mut W {
255        self.variant(HCLKPRESC_A::DIV16)
256    }
257}
258impl R {
259    #[doc = "Bits 0:2 - Clock Select"]
260    #[inline(always)]
261    pub fn clksel(&self) -> CLKSEL_R {
262        CLKSEL_R::new((self.bits & 7) as u8)
263    }
264    #[doc = "Bit 10 - PCLK Prescaler"]
265    #[inline(always)]
266    pub fn pclkpresc(&self) -> PCLKPRESC_R {
267        PCLKPRESC_R::new(((self.bits >> 10) & 1) != 0)
268    }
269    #[doc = "Bits 12:15 - HCLK Prescaler"]
270    #[inline(always)]
271    pub fn hclkpresc(&self) -> HCLKPRESC_R {
272        HCLKPRESC_R::new(((self.bits >> 12) & 0x0f) as u8)
273    }
274}
275impl W {
276    #[doc = "Bits 0:2 - Clock Select"]
277    #[inline(always)]
278    #[must_use]
279    pub fn clksel(&mut self) -> CLKSEL_W<0> {
280        CLKSEL_W::new(self)
281    }
282    #[doc = "Bit 10 - PCLK Prescaler"]
283    #[inline(always)]
284    #[must_use]
285    pub fn pclkpresc(&mut self) -> PCLKPRESC_W<10> {
286        PCLKPRESC_W::new(self)
287    }
288    #[doc = "Bits 12:15 - HCLK Prescaler"]
289    #[inline(always)]
290    #[must_use]
291    pub fn hclkpresc(&mut self) -> HCLKPRESC_W<12> {
292        HCLKPRESC_W::new(self)
293    }
294    #[doc = "Writes raw bits to the register."]
295    #[inline(always)]
296    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
297        self.0.bits(bits);
298        self
299    }
300}
301#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sysclkctrl](index.html) module"]
302pub struct SYSCLKCTRL_SPEC;
303impl crate::RegisterSpec for SYSCLKCTRL_SPEC {
304    type Ux = u32;
305}
306#[doc = "`read()` method returns [sysclkctrl::R](R) reader structure"]
307impl crate::Readable for SYSCLKCTRL_SPEC {
308    type Reader = R;
309}
310#[doc = "`write(|w| ..)` method takes [sysclkctrl::W](W) writer structure"]
311impl crate::Writable for SYSCLKCTRL_SPEC {
312    type Writer = W;
313    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
314    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
315}
316#[doc = "`reset()` method sets SYSCLKCTRL to value 0x01"]
317impl crate::Resettable for SYSCLKCTRL_SPEC {
318    const RESET_VALUE: Self::Ux = 0x01;
319}
efm32pg22_pac/efm32pg22c200/cmu_s/sysclkctrl.rs

efm32pg22_pac/efm32pg22c200/cmu_s/
sysclkctrl.rs
