efm32pg22_pac/efm32pg22c200/cmu_s/
euart0clkctrl.rs

1#[doc = "Register `EUART0CLKCTRL` reader"]
2pub struct R(crate::R<EUART0CLKCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<EUART0CLKCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<EUART0CLKCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<EUART0CLKCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `EUART0CLKCTRL` writer"]
17pub struct W(crate::W<EUART0CLKCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<EUART0CLKCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<EUART0CLKCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<EUART0CLKCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CLKSEL` reader - Clock Select"]
38pub type CLKSEL_R = crate::FieldReader<u8, CLKSEL_A>;
39#[doc = "Clock Select\n\nValue on reset: 1"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CLKSEL_A {
43    #[doc = "0: UART is not clocked"]
44    DISABLED = 0,
45    #[doc = "1: EM01GRPACLK is clocking UART"]
46    EM01GRPACLK = 1,
47    #[doc = "2: EM23GRPACLK is clocking UART"]
48    EM23GRPACLK = 2,
49}
50impl From<CLKSEL_A> for u8 {
51    #[inline(always)]
52    fn from(variant: CLKSEL_A) -> Self {
53        variant as _
54    }
55}
56impl CLKSEL_R {
57    #[doc = "Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> Option<CLKSEL_A> {
60        match self.bits {
61            0 => Some(CLKSEL_A::DISABLED),
62            1 => Some(CLKSEL_A::EM01GRPACLK),
63            2 => Some(CLKSEL_A::EM23GRPACLK),
64            _ => None,
65        }
66    }
67    #[doc = "Checks if the value of the field is `DISABLED`"]
68    #[inline(always)]
69    pub fn is_disabled(&self) -> bool {
70        *self == CLKSEL_A::DISABLED
71    }
72    #[doc = "Checks if the value of the field is `EM01GRPACLK`"]
73    #[inline(always)]
74    pub fn is_em01grpaclk(&self) -> bool {
75        *self == CLKSEL_A::EM01GRPACLK
76    }
77    #[doc = "Checks if the value of the field is `EM23GRPACLK`"]
78    #[inline(always)]
79    pub fn is_em23grpaclk(&self) -> bool {
80        *self == CLKSEL_A::EM23GRPACLK
81    }
82}
83#[doc = "Field `CLKSEL` writer - Clock Select"]
84pub type CLKSEL_W<'a, const O: u8> =
85    crate::FieldWriter<'a, u32, EUART0CLKCTRL_SPEC, u8, CLKSEL_A, 2, O>;
86impl<'a, const O: u8> CLKSEL_W<'a, O> {
87    #[doc = "UART is not clocked"]
88    #[inline(always)]
89    pub fn disabled(self) -> &'a mut W {
90        self.variant(CLKSEL_A::DISABLED)
91    }
92    #[doc = "EM01GRPACLK is clocking UART"]
93    #[inline(always)]
94    pub fn em01grpaclk(self) -> &'a mut W {
95        self.variant(CLKSEL_A::EM01GRPACLK)
96    }
97    #[doc = "EM23GRPACLK is clocking UART"]
98    #[inline(always)]
99    pub fn em23grpaclk(self) -> &'a mut W {
100        self.variant(CLKSEL_A::EM23GRPACLK)
101    }
102}
103impl R {
104    #[doc = "Bits 0:1 - Clock Select"]
105    #[inline(always)]
106    pub fn clksel(&self) -> CLKSEL_R {
107        CLKSEL_R::new((self.bits & 3) as u8)
108    }
109}
110impl W {
111    #[doc = "Bits 0:1 - Clock Select"]
112    #[inline(always)]
113    #[must_use]
114    pub fn clksel(&mut self) -> CLKSEL_W<0> {
115        CLKSEL_W::new(self)
116    }
117    #[doc = "Writes raw bits to the register."]
118    #[inline(always)]
119    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
120        self.0.bits(bits);
121        self
122    }
123}
124#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [euart0clkctrl](index.html) module"]
125pub struct EUART0CLKCTRL_SPEC;
126impl crate::RegisterSpec for EUART0CLKCTRL_SPEC {
127    type Ux = u32;
128}
129#[doc = "`read()` method returns [euart0clkctrl::R](R) reader structure"]
130impl crate::Readable for EUART0CLKCTRL_SPEC {
131    type Reader = R;
132}
133#[doc = "`write(|w| ..)` method takes [euart0clkctrl::W](W) writer structure"]
134impl crate::Writable for EUART0CLKCTRL_SPEC {
135    type Writer = W;
136    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
137    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
138}
139#[doc = "`reset()` method sets EUART0CLKCTRL to value 0x01"]
140impl crate::Resettable for EUART0CLKCTRL_SPEC {
141    const RESET_VALUE: Self::Ux = 0x01;
142}
efm32pg22_pac/efm32pg22c200/cmu_s/euart0clkctrl.rs

efm32pg22_pac/efm32pg22c200/cmu_s/
euart0clkctrl.rs
