1#[doc = "Register `CLKEN0` reader"]
2pub struct R(crate::R<CLKEN0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CLKEN0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CLKEN0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CLKEN0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CLKEN0` writer"]
17pub struct W(crate::W<CLKEN0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CLKEN0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CLKEN0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CLKEN0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `LDMA` reader - Enable Bus Clock"]
38pub type LDMA_R = crate::BitReader<bool>;
39#[doc = "Field `LDMA` writer - Enable Bus Clock"]
40pub type LDMA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
41#[doc = "Field `LDMAXBAR` reader - Enable Bus Clock"]
42pub type LDMAXBAR_R = crate::BitReader<bool>;
43#[doc = "Field `LDMAXBAR` writer - Enable Bus Clock"]
44pub type LDMAXBAR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
45#[doc = "Field `GPCRC` reader - Enable Bus Clock"]
46pub type GPCRC_R = crate::BitReader<bool>;
47#[doc = "Field `GPCRC` writer - Enable Bus Clock"]
48pub type GPCRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
49#[doc = "Field `TIMER0` reader - Enable Bus Clock"]
50pub type TIMER0_R = crate::BitReader<bool>;
51#[doc = "Field `TIMER0` writer - Enable Bus Clock"]
52pub type TIMER0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
53#[doc = "Field `TIMER1` reader - Enable Bus Clock"]
54pub type TIMER1_R = crate::BitReader<bool>;
55#[doc = "Field `TIMER1` writer - Enable Bus Clock"]
56pub type TIMER1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
57#[doc = "Field `TIMER2` reader - Enable Bus Clock"]
58pub type TIMER2_R = crate::BitReader<bool>;
59#[doc = "Field `TIMER2` writer - Enable Bus Clock"]
60pub type TIMER2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
61#[doc = "Field `TIMER3` reader - Enable Bus Clock"]
62pub type TIMER3_R = crate::BitReader<bool>;
63#[doc = "Field `TIMER3` writer - Enable Bus Clock"]
64pub type TIMER3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
65#[doc = "Field `USART0` reader - Enable Bus Clock"]
66pub type USART0_R = crate::BitReader<bool>;
67#[doc = "Field `USART0` writer - Enable Bus Clock"]
68pub type USART0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
69#[doc = "Field `USART1` reader - Enable Bus Clock"]
70pub type USART1_R = crate::BitReader<bool>;
71#[doc = "Field `USART1` writer - Enable Bus Clock"]
72pub type USART1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
73#[doc = "Field `IADC0` reader - Enable Bus Clock"]
74pub type IADC0_R = crate::BitReader<bool>;
75#[doc = "Field `IADC0` writer - Enable Bus Clock"]
76pub type IADC0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
77#[doc = "Field `AMUXCP0` reader - Enable Bus Clock"]
78pub type AMUXCP0_R = crate::BitReader<bool>;
79#[doc = "Field `AMUXCP0` writer - Enable Bus Clock"]
80pub type AMUXCP0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
81#[doc = "Field `LETIMER0` reader - Enable Bus Clock"]
82pub type LETIMER0_R = crate::BitReader<bool>;
83#[doc = "Field `LETIMER0` writer - Enable Bus Clock"]
84pub type LETIMER0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
85#[doc = "Field `WDOG0` reader - Enable Bus Clock"]
86pub type WDOG0_R = crate::BitReader<bool>;
87#[doc = "Field `WDOG0` writer - Enable Bus Clock"]
88pub type WDOG0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
89#[doc = "Field `I2C0` reader - Enable Bus Clock"]
90pub type I2C0_R = crate::BitReader<bool>;
91#[doc = "Field `I2C0` writer - Enable Bus Clock"]
92pub type I2C0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
93#[doc = "Field `I2C1` reader - Enable Bus Clock"]
94pub type I2C1_R = crate::BitReader<bool>;
95#[doc = "Field `I2C1` writer - Enable Bus Clock"]
96pub type I2C1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
97#[doc = "Field `SYSCFG` reader - Enable Bus Clock"]
98pub type SYSCFG_R = crate::BitReader<bool>;
99#[doc = "Field `SYSCFG` writer - Enable Bus Clock"]
100pub type SYSCFG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
101#[doc = "Field `DPLL0` reader - Enable Bus Clock"]
102pub type DPLL0_R = crate::BitReader<bool>;
103#[doc = "Field `DPLL0` writer - Enable Bus Clock"]
104pub type DPLL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
105#[doc = "Field `HFRCO0` reader - Enable Bus Clock"]
106pub type HFRCO0_R = crate::BitReader<bool>;
107#[doc = "Field `HFRCO0` writer - Enable Bus Clock"]
108pub type HFRCO0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
109#[doc = "Field `HFXO0` reader - Enable Bus Clock"]
110pub type HFXO0_R = crate::BitReader<bool>;
111#[doc = "Field `HFXO0` writer - Enable Bus Clock"]
112pub type HFXO0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
113#[doc = "Field `FSRCO` reader - Enable Bus Clock"]
114pub type FSRCO_R = crate::BitReader<bool>;
115#[doc = "Field `FSRCO` writer - Enable Bus Clock"]
116pub type FSRCO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
117#[doc = "Field `LFRCO` reader - Enable Bus Clock"]
118pub type LFRCO_R = crate::BitReader<bool>;
119#[doc = "Field `LFRCO` writer - Enable Bus Clock"]
120pub type LFRCO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
121#[doc = "Field `LFXO` reader - Enable Bus Clock"]
122pub type LFXO_R = crate::BitReader<bool>;
123#[doc = "Field `LFXO` writer - Enable Bus Clock"]
124pub type LFXO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
125#[doc = "Field `ULFRCO` reader - Enable Bus Clock"]
126pub type ULFRCO_R = crate::BitReader<bool>;
127#[doc = "Field `ULFRCO` writer - Enable Bus Clock"]
128pub type ULFRCO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
129#[doc = "Field `EUART0` reader - Enable Bus Clock"]
130pub type EUART0_R = crate::BitReader<bool>;
131#[doc = "Field `EUART0` writer - Enable Bus Clock"]
132pub type EUART0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
133#[doc = "Field `PDM` reader - Enable Bus Clock"]
134pub type PDM_R = crate::BitReader<bool>;
135#[doc = "Field `PDM` writer - Enable Bus Clock"]
136pub type PDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
137#[doc = "Field `GPIO` reader - Enable Bus Clock"]
138pub type GPIO_R = crate::BitReader<bool>;
139#[doc = "Field `GPIO` writer - Enable Bus Clock"]
140pub type GPIO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
141#[doc = "Field `PRS` reader - Enable Bus Clock"]
142pub type PRS_R = crate::BitReader<bool>;
143#[doc = "Field `PRS` writer - Enable Bus Clock"]
144pub type PRS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
145#[doc = "Field `BURAM` reader - Enable Bus Clock"]
146pub type BURAM_R = crate::BitReader<bool>;
147#[doc = "Field `BURAM` writer - Enable Bus Clock"]
148pub type BURAM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
149#[doc = "Field `BURTC` reader - Enable Bus Clock"]
150pub type BURTC_R = crate::BitReader<bool>;
151#[doc = "Field `BURTC` writer - Enable Bus Clock"]
152pub type BURTC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
153#[doc = "Field `RTCC` reader - Enable Bus Clock"]
154pub type RTCC_R = crate::BitReader<bool>;
155#[doc = "Field `RTCC` writer - Enable Bus Clock"]
156pub type RTCC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
157#[doc = "Field `DCDC` reader - Enable Bus Clock"]
158pub type DCDC_R = crate::BitReader<bool>;
159#[doc = "Field `DCDC` writer - Enable Bus Clock"]
160pub type DCDC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN0_SPEC, bool, O>;
161impl R {
162 #[doc = "Bit 0 - Enable Bus Clock"]
163 #[inline(always)]
164 pub fn ldma(&self) -> LDMA_R {
165 LDMA_R::new((self.bits & 1) != 0)
166 }
167 #[doc = "Bit 1 - Enable Bus Clock"]
168 #[inline(always)]
169 pub fn ldmaxbar(&self) -> LDMAXBAR_R {
170 LDMAXBAR_R::new(((self.bits >> 1) & 1) != 0)
171 }
172 #[doc = "Bit 3 - Enable Bus Clock"]
173 #[inline(always)]
174 pub fn gpcrc(&self) -> GPCRC_R {
175 GPCRC_R::new(((self.bits >> 3) & 1) != 0)
176 }
177 #[doc = "Bit 4 - Enable Bus Clock"]
178 #[inline(always)]
179 pub fn timer0(&self) -> TIMER0_R {
180 TIMER0_R::new(((self.bits >> 4) & 1) != 0)
181 }
182 #[doc = "Bit 5 - Enable Bus Clock"]
183 #[inline(always)]
184 pub fn timer1(&self) -> TIMER1_R {
185 TIMER1_R::new(((self.bits >> 5) & 1) != 0)
186 }
187 #[doc = "Bit 6 - Enable Bus Clock"]
188 #[inline(always)]
189 pub fn timer2(&self) -> TIMER2_R {
190 TIMER2_R::new(((self.bits >> 6) & 1) != 0)
191 }
192 #[doc = "Bit 7 - Enable Bus Clock"]
193 #[inline(always)]
194 pub fn timer3(&self) -> TIMER3_R {
195 TIMER3_R::new(((self.bits >> 7) & 1) != 0)
196 }
197 #[doc = "Bit 8 - Enable Bus Clock"]
198 #[inline(always)]
199 pub fn usart0(&self) -> USART0_R {
200 USART0_R::new(((self.bits >> 8) & 1) != 0)
201 }
202 #[doc = "Bit 9 - Enable Bus Clock"]
203 #[inline(always)]
204 pub fn usart1(&self) -> USART1_R {
205 USART1_R::new(((self.bits >> 9) & 1) != 0)
206 }
207 #[doc = "Bit 10 - Enable Bus Clock"]
208 #[inline(always)]
209 pub fn iadc0(&self) -> IADC0_R {
210 IADC0_R::new(((self.bits >> 10) & 1) != 0)
211 }
212 #[doc = "Bit 11 - Enable Bus Clock"]
213 #[inline(always)]
214 pub fn amuxcp0(&self) -> AMUXCP0_R {
215 AMUXCP0_R::new(((self.bits >> 11) & 1) != 0)
216 }
217 #[doc = "Bit 12 - Enable Bus Clock"]
218 #[inline(always)]
219 pub fn letimer0(&self) -> LETIMER0_R {
220 LETIMER0_R::new(((self.bits >> 12) & 1) != 0)
221 }
222 #[doc = "Bit 13 - Enable Bus Clock"]
223 #[inline(always)]
224 pub fn wdog0(&self) -> WDOG0_R {
225 WDOG0_R::new(((self.bits >> 13) & 1) != 0)
226 }
227 #[doc = "Bit 14 - Enable Bus Clock"]
228 #[inline(always)]
229 pub fn i2c0(&self) -> I2C0_R {
230 I2C0_R::new(((self.bits >> 14) & 1) != 0)
231 }
232 #[doc = "Bit 15 - Enable Bus Clock"]
233 #[inline(always)]
234 pub fn i2c1(&self) -> I2C1_R {
235 I2C1_R::new(((self.bits >> 15) & 1) != 0)
236 }
237 #[doc = "Bit 16 - Enable Bus Clock"]
238 #[inline(always)]
239 pub fn syscfg(&self) -> SYSCFG_R {
240 SYSCFG_R::new(((self.bits >> 16) & 1) != 0)
241 }
242 #[doc = "Bit 17 - Enable Bus Clock"]
243 #[inline(always)]
244 pub fn dpll0(&self) -> DPLL0_R {
245 DPLL0_R::new(((self.bits >> 17) & 1) != 0)
246 }
247 #[doc = "Bit 18 - Enable Bus Clock"]
248 #[inline(always)]
249 pub fn hfrco0(&self) -> HFRCO0_R {
250 HFRCO0_R::new(((self.bits >> 18) & 1) != 0)
251 }
252 #[doc = "Bit 19 - Enable Bus Clock"]
253 #[inline(always)]
254 pub fn hfxo0(&self) -> HFXO0_R {
255 HFXO0_R::new(((self.bits >> 19) & 1) != 0)
256 }
257 #[doc = "Bit 20 - Enable Bus Clock"]
258 #[inline(always)]
259 pub fn fsrco(&self) -> FSRCO_R {
260 FSRCO_R::new(((self.bits >> 20) & 1) != 0)
261 }
262 #[doc = "Bit 21 - Enable Bus Clock"]
263 #[inline(always)]
264 pub fn lfrco(&self) -> LFRCO_R {
265 LFRCO_R::new(((self.bits >> 21) & 1) != 0)
266 }
267 #[doc = "Bit 22 - Enable Bus Clock"]
268 #[inline(always)]
269 pub fn lfxo(&self) -> LFXO_R {
270 LFXO_R::new(((self.bits >> 22) & 1) != 0)
271 }
272 #[doc = "Bit 23 - Enable Bus Clock"]
273 #[inline(always)]
274 pub fn ulfrco(&self) -> ULFRCO_R {
275 ULFRCO_R::new(((self.bits >> 23) & 1) != 0)
276 }
277 #[doc = "Bit 24 - Enable Bus Clock"]
278 #[inline(always)]
279 pub fn euart0(&self) -> EUART0_R {
280 EUART0_R::new(((self.bits >> 24) & 1) != 0)
281 }
282 #[doc = "Bit 25 - Enable Bus Clock"]
283 #[inline(always)]
284 pub fn pdm(&self) -> PDM_R {
285 PDM_R::new(((self.bits >> 25) & 1) != 0)
286 }
287 #[doc = "Bit 26 - Enable Bus Clock"]
288 #[inline(always)]
289 pub fn gpio(&self) -> GPIO_R {
290 GPIO_R::new(((self.bits >> 26) & 1) != 0)
291 }
292 #[doc = "Bit 27 - Enable Bus Clock"]
293 #[inline(always)]
294 pub fn prs(&self) -> PRS_R {
295 PRS_R::new(((self.bits >> 27) & 1) != 0)
296 }
297 #[doc = "Bit 28 - Enable Bus Clock"]
298 #[inline(always)]
299 pub fn buram(&self) -> BURAM_R {
300 BURAM_R::new(((self.bits >> 28) & 1) != 0)
301 }
302 #[doc = "Bit 29 - Enable Bus Clock"]
303 #[inline(always)]
304 pub fn burtc(&self) -> BURTC_R {
305 BURTC_R::new(((self.bits >> 29) & 1) != 0)
306 }
307 #[doc = "Bit 30 - Enable Bus Clock"]
308 #[inline(always)]
309 pub fn rtcc(&self) -> RTCC_R {
310 RTCC_R::new(((self.bits >> 30) & 1) != 0)
311 }
312 #[doc = "Bit 31 - Enable Bus Clock"]
313 #[inline(always)]
314 pub fn dcdc(&self) -> DCDC_R {
315 DCDC_R::new(((self.bits >> 31) & 1) != 0)
316 }
317}
318impl W {
319 #[doc = "Bit 0 - Enable Bus Clock"]
320 #[inline(always)]
321 #[must_use]
322 pub fn ldma(&mut self) -> LDMA_W<0> {
323 LDMA_W::new(self)
324 }
325 #[doc = "Bit 1 - Enable Bus Clock"]
326 #[inline(always)]
327 #[must_use]
328 pub fn ldmaxbar(&mut self) -> LDMAXBAR_W<1> {
329 LDMAXBAR_W::new(self)
330 }
331 #[doc = "Bit 3 - Enable Bus Clock"]
332 #[inline(always)]
333 #[must_use]
334 pub fn gpcrc(&mut self) -> GPCRC_W<3> {
335 GPCRC_W::new(self)
336 }
337 #[doc = "Bit 4 - Enable Bus Clock"]
338 #[inline(always)]
339 #[must_use]
340 pub fn timer0(&mut self) -> TIMER0_W<4> {
341 TIMER0_W::new(self)
342 }
343 #[doc = "Bit 5 - Enable Bus Clock"]
344 #[inline(always)]
345 #[must_use]
346 pub fn timer1(&mut self) -> TIMER1_W<5> {
347 TIMER1_W::new(self)
348 }
349 #[doc = "Bit 6 - Enable Bus Clock"]
350 #[inline(always)]
351 #[must_use]
352 pub fn timer2(&mut self) -> TIMER2_W<6> {
353 TIMER2_W::new(self)
354 }
355 #[doc = "Bit 7 - Enable Bus Clock"]
356 #[inline(always)]
357 #[must_use]
358 pub fn timer3(&mut self) -> TIMER3_W<7> {
359 TIMER3_W::new(self)
360 }
361 #[doc = "Bit 8 - Enable Bus Clock"]
362 #[inline(always)]
363 #[must_use]
364 pub fn usart0(&mut self) -> USART0_W<8> {
365 USART0_W::new(self)
366 }
367 #[doc = "Bit 9 - Enable Bus Clock"]
368 #[inline(always)]
369 #[must_use]
370 pub fn usart1(&mut self) -> USART1_W<9> {
371 USART1_W::new(self)
372 }
373 #[doc = "Bit 10 - Enable Bus Clock"]
374 #[inline(always)]
375 #[must_use]
376 pub fn iadc0(&mut self) -> IADC0_W<10> {
377 IADC0_W::new(self)
378 }
379 #[doc = "Bit 11 - Enable Bus Clock"]
380 #[inline(always)]
381 #[must_use]
382 pub fn amuxcp0(&mut self) -> AMUXCP0_W<11> {
383 AMUXCP0_W::new(self)
384 }
385 #[doc = "Bit 12 - Enable Bus Clock"]
386 #[inline(always)]
387 #[must_use]
388 pub fn letimer0(&mut self) -> LETIMER0_W<12> {
389 LETIMER0_W::new(self)
390 }
391 #[doc = "Bit 13 - Enable Bus Clock"]
392 #[inline(always)]
393 #[must_use]
394 pub fn wdog0(&mut self) -> WDOG0_W<13> {
395 WDOG0_W::new(self)
396 }
397 #[doc = "Bit 14 - Enable Bus Clock"]
398 #[inline(always)]
399 #[must_use]
400 pub fn i2c0(&mut self) -> I2C0_W<14> {
401 I2C0_W::new(self)
402 }
403 #[doc = "Bit 15 - Enable Bus Clock"]
404 #[inline(always)]
405 #[must_use]
406 pub fn i2c1(&mut self) -> I2C1_W<15> {
407 I2C1_W::new(self)
408 }
409 #[doc = "Bit 16 - Enable Bus Clock"]
410 #[inline(always)]
411 #[must_use]
412 pub fn syscfg(&mut self) -> SYSCFG_W<16> {
413 SYSCFG_W::new(self)
414 }
415 #[doc = "Bit 17 - Enable Bus Clock"]
416 #[inline(always)]
417 #[must_use]
418 pub fn dpll0(&mut self) -> DPLL0_W<17> {
419 DPLL0_W::new(self)
420 }
421 #[doc = "Bit 18 - Enable Bus Clock"]
422 #[inline(always)]
423 #[must_use]
424 pub fn hfrco0(&mut self) -> HFRCO0_W<18> {
425 HFRCO0_W::new(self)
426 }
427 #[doc = "Bit 19 - Enable Bus Clock"]
428 #[inline(always)]
429 #[must_use]
430 pub fn hfxo0(&mut self) -> HFXO0_W<19> {
431 HFXO0_W::new(self)
432 }
433 #[doc = "Bit 20 - Enable Bus Clock"]
434 #[inline(always)]
435 #[must_use]
436 pub fn fsrco(&mut self) -> FSRCO_W<20> {
437 FSRCO_W::new(self)
438 }
439 #[doc = "Bit 21 - Enable Bus Clock"]
440 #[inline(always)]
441 #[must_use]
442 pub fn lfrco(&mut self) -> LFRCO_W<21> {
443 LFRCO_W::new(self)
444 }
445 #[doc = "Bit 22 - Enable Bus Clock"]
446 #[inline(always)]
447 #[must_use]
448 pub fn lfxo(&mut self) -> LFXO_W<22> {
449 LFXO_W::new(self)
450 }
451 #[doc = "Bit 23 - Enable Bus Clock"]
452 #[inline(always)]
453 #[must_use]
454 pub fn ulfrco(&mut self) -> ULFRCO_W<23> {
455 ULFRCO_W::new(self)
456 }
457 #[doc = "Bit 24 - Enable Bus Clock"]
458 #[inline(always)]
459 #[must_use]
460 pub fn euart0(&mut self) -> EUART0_W<24> {
461 EUART0_W::new(self)
462 }
463 #[doc = "Bit 25 - Enable Bus Clock"]
464 #[inline(always)]
465 #[must_use]
466 pub fn pdm(&mut self) -> PDM_W<25> {
467 PDM_W::new(self)
468 }
469 #[doc = "Bit 26 - Enable Bus Clock"]
470 #[inline(always)]
471 #[must_use]
472 pub fn gpio(&mut self) -> GPIO_W<26> {
473 GPIO_W::new(self)
474 }
475 #[doc = "Bit 27 - Enable Bus Clock"]
476 #[inline(always)]
477 #[must_use]
478 pub fn prs(&mut self) -> PRS_W<27> {
479 PRS_W::new(self)
480 }
481 #[doc = "Bit 28 - Enable Bus Clock"]
482 #[inline(always)]
483 #[must_use]
484 pub fn buram(&mut self) -> BURAM_W<28> {
485 BURAM_W::new(self)
486 }
487 #[doc = "Bit 29 - Enable Bus Clock"]
488 #[inline(always)]
489 #[must_use]
490 pub fn burtc(&mut self) -> BURTC_W<29> {
491 BURTC_W::new(self)
492 }
493 #[doc = "Bit 30 - Enable Bus Clock"]
494 #[inline(always)]
495 #[must_use]
496 pub fn rtcc(&mut self) -> RTCC_W<30> {
497 RTCC_W::new(self)
498 }
499 #[doc = "Bit 31 - Enable Bus Clock"]
500 #[inline(always)]
501 #[must_use]
502 pub fn dcdc(&mut self) -> DCDC_W<31> {
503 DCDC_W::new(self)
504 }
505 #[doc = "Writes raw bits to the register."]
506 #[inline(always)]
507 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
508 self.0.bits(bits);
509 self
510 }
511}
512#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clken0](index.html) module"]
513pub struct CLKEN0_SPEC;
514impl crate::RegisterSpec for CLKEN0_SPEC {
515 type Ux = u32;
516}
517#[doc = "`read()` method returns [clken0::R](R) reader structure"]
518impl crate::Readable for CLKEN0_SPEC {
519 type Reader = R;
520}
521#[doc = "`write(|w| ..)` method takes [clken0::W](W) writer structure"]
522impl crate::Writable for CLKEN0_SPEC {
523 type Writer = W;
524 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
525 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
526}
527#[doc = "`reset()` method sets CLKEN0 to value 0"]
528impl crate::Resettable for CLKEN0_SPEC {
529 const RESET_VALUE: Self::Ux = 0;
530}