efm32pg22_pac/efm32pg22c200/cmu_ns/
wdog0clkctrl.rs

1#[doc = "Register `WDOG0CLKCTRL` reader"]
2pub struct R(crate::R<WDOG0CLKCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<WDOG0CLKCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<WDOG0CLKCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<WDOG0CLKCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `WDOG0CLKCTRL` writer"]
17pub struct W(crate::W<WDOG0CLKCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<WDOG0CLKCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<WDOG0CLKCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<WDOG0CLKCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CLKSEL` reader - Clock Select"]
38pub type CLKSEL_R = crate::FieldReader<u8, CLKSEL_A>;
39#[doc = "Clock Select\n\nValue on reset: 1"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CLKSEL_A {
43    #[doc = "1: LFRCO is clocking WDOG0CLK"]
44    LFRCO = 1,
45    #[doc = "2: LFXO is clocking WDOG0CLK"]
46    LFXO = 2,
47    #[doc = "3: ULFRCO is clocking WDOG0CLK"]
48    ULFRCO = 3,
49    #[doc = "4: HCLKDIV1024 is clocking WDOG0CLK"]
50    HCLKDIV1024 = 4,
51}
52impl From<CLKSEL_A> for u8 {
53    #[inline(always)]
54    fn from(variant: CLKSEL_A) -> Self {
55        variant as _
56    }
57}
58impl CLKSEL_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> Option<CLKSEL_A> {
62        match self.bits {
63            1 => Some(CLKSEL_A::LFRCO),
64            2 => Some(CLKSEL_A::LFXO),
65            3 => Some(CLKSEL_A::ULFRCO),
66            4 => Some(CLKSEL_A::HCLKDIV1024),
67            _ => None,
68        }
69    }
70    #[doc = "Checks if the value of the field is `LFRCO`"]
71    #[inline(always)]
72    pub fn is_lfrco(&self) -> bool {
73        *self == CLKSEL_A::LFRCO
74    }
75    #[doc = "Checks if the value of the field is `LFXO`"]
76    #[inline(always)]
77    pub fn is_lfxo(&self) -> bool {
78        *self == CLKSEL_A::LFXO
79    }
80    #[doc = "Checks if the value of the field is `ULFRCO`"]
81    #[inline(always)]
82    pub fn is_ulfrco(&self) -> bool {
83        *self == CLKSEL_A::ULFRCO
84    }
85    #[doc = "Checks if the value of the field is `HCLKDIV1024`"]
86    #[inline(always)]
87    pub fn is_hclkdiv1024(&self) -> bool {
88        *self == CLKSEL_A::HCLKDIV1024
89    }
90}
91#[doc = "Field `CLKSEL` writer - Clock Select"]
92pub type CLKSEL_W<'a, const O: u8> =
93    crate::FieldWriter<'a, u32, WDOG0CLKCTRL_SPEC, u8, CLKSEL_A, 3, O>;
94impl<'a, const O: u8> CLKSEL_W<'a, O> {
95    #[doc = "LFRCO is clocking WDOG0CLK"]
96    #[inline(always)]
97    pub fn lfrco(self) -> &'a mut W {
98        self.variant(CLKSEL_A::LFRCO)
99    }
100    #[doc = "LFXO is clocking WDOG0CLK"]
101    #[inline(always)]
102    pub fn lfxo(self) -> &'a mut W {
103        self.variant(CLKSEL_A::LFXO)
104    }
105    #[doc = "ULFRCO is clocking WDOG0CLK"]
106    #[inline(always)]
107    pub fn ulfrco(self) -> &'a mut W {
108        self.variant(CLKSEL_A::ULFRCO)
109    }
110    #[doc = "HCLKDIV1024 is clocking WDOG0CLK"]
111    #[inline(always)]
112    pub fn hclkdiv1024(self) -> &'a mut W {
113        self.variant(CLKSEL_A::HCLKDIV1024)
114    }
115}
116impl R {
117    #[doc = "Bits 0:2 - Clock Select"]
118    #[inline(always)]
119    pub fn clksel(&self) -> CLKSEL_R {
120        CLKSEL_R::new((self.bits & 7) as u8)
121    }
122}
123impl W {
124    #[doc = "Bits 0:2 - Clock Select"]
125    #[inline(always)]
126    #[must_use]
127    pub fn clksel(&mut self) -> CLKSEL_W<0> {
128        CLKSEL_W::new(self)
129    }
130    #[doc = "Writes raw bits to the register."]
131    #[inline(always)]
132    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
133        self.0.bits(bits);
134        self
135    }
136}
137#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdog0clkctrl](index.html) module"]
138pub struct WDOG0CLKCTRL_SPEC;
139impl crate::RegisterSpec for WDOG0CLKCTRL_SPEC {
140    type Ux = u32;
141}
142#[doc = "`read()` method returns [wdog0clkctrl::R](R) reader structure"]
143impl crate::Readable for WDOG0CLKCTRL_SPEC {
144    type Reader = R;
145}
146#[doc = "`write(|w| ..)` method takes [wdog0clkctrl::W](W) writer structure"]
147impl crate::Writable for WDOG0CLKCTRL_SPEC {
148    type Writer = W;
149    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
150    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
151}
152#[doc = "`reset()` method sets WDOG0CLKCTRL to value 0x01"]
153impl crate::Resettable for WDOG0CLKCTRL_SPEC {
154    const RESET_VALUE: Self::Ux = 0x01;
155}
efm32pg22_pac/efm32pg22c200/cmu_ns/wdog0clkctrl.rs

efm32pg22_pac/efm32pg22c200/cmu_ns/
wdog0clkctrl.rs
