efm32pg22_pac/efm32pg22c200/cmu_ns/
clken1.rs

1#[doc = "Register `CLKEN1` reader"]
2pub struct R(crate::R<CLKEN1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLKEN1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLKEN1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLKEN1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CLKEN1` writer"]
17pub struct W(crate::W<CLKEN1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLKEN1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLKEN1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLKEN1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CRYPTOACC` reader - Enable Bus Clock"]
38pub type CRYPTOACC_R = crate::BitReader<bool>;
39#[doc = "Field `CRYPTOACC` writer - Enable Bus Clock"]
40pub type CRYPTOACC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN1_SPEC, bool, O>;
41#[doc = "Field `SMU` reader - Enable Bus Clock"]
42pub type SMU_R = crate::BitReader<bool>;
43#[doc = "Field `SMU` writer - Enable Bus Clock"]
44pub type SMU_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN1_SPEC, bool, O>;
45#[doc = "Field `ICACHE0` reader - Enable Bus Clock"]
46pub type ICACHE0_R = crate::BitReader<bool>;
47#[doc = "Field `ICACHE0` writer - Enable Bus Clock"]
48pub type ICACHE0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN1_SPEC, bool, O>;
49#[doc = "Field `MSC` reader - Enable Bus Clock"]
50pub type MSC_R = crate::BitReader<bool>;
51#[doc = "Field `MSC` writer - Enable Bus Clock"]
52pub type MSC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN1_SPEC, bool, O>;
53#[doc = "Field `TIMER4` reader - Enable Bus Clock"]
54pub type TIMER4_R = crate::BitReader<bool>;
55#[doc = "Field `TIMER4` writer - Enable Bus Clock"]
56pub type TIMER4_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKEN1_SPEC, bool, O>;
57impl R {
58    #[doc = "Bit 13 - Enable Bus Clock"]
59    #[inline(always)]
60    pub fn cryptoacc(&self) -> CRYPTOACC_R {
61        CRYPTOACC_R::new(((self.bits >> 13) & 1) != 0)
62    }
63    #[doc = "Bit 15 - Enable Bus Clock"]
64    #[inline(always)]
65    pub fn smu(&self) -> SMU_R {
66        SMU_R::new(((self.bits >> 15) & 1) != 0)
67    }
68    #[doc = "Bit 16 - Enable Bus Clock"]
69    #[inline(always)]
70    pub fn icache0(&self) -> ICACHE0_R {
71        ICACHE0_R::new(((self.bits >> 16) & 1) != 0)
72    }
73    #[doc = "Bit 17 - Enable Bus Clock"]
74    #[inline(always)]
75    pub fn msc(&self) -> MSC_R {
76        MSC_R::new(((self.bits >> 17) & 1) != 0)
77    }
78    #[doc = "Bit 18 - Enable Bus Clock"]
79    #[inline(always)]
80    pub fn timer4(&self) -> TIMER4_R {
81        TIMER4_R::new(((self.bits >> 18) & 1) != 0)
82    }
83}
84impl W {
85    #[doc = "Bit 13 - Enable Bus Clock"]
86    #[inline(always)]
87    #[must_use]
88    pub fn cryptoacc(&mut self) -> CRYPTOACC_W<13> {
89        CRYPTOACC_W::new(self)
90    }
91    #[doc = "Bit 15 - Enable Bus Clock"]
92    #[inline(always)]
93    #[must_use]
94    pub fn smu(&mut self) -> SMU_W<15> {
95        SMU_W::new(self)
96    }
97    #[doc = "Bit 16 - Enable Bus Clock"]
98    #[inline(always)]
99    #[must_use]
100    pub fn icache0(&mut self) -> ICACHE0_W<16> {
101        ICACHE0_W::new(self)
102    }
103    #[doc = "Bit 17 - Enable Bus Clock"]
104    #[inline(always)]
105    #[must_use]
106    pub fn msc(&mut self) -> MSC_W<17> {
107        MSC_W::new(self)
108    }
109    #[doc = "Bit 18 - Enable Bus Clock"]
110    #[inline(always)]
111    #[must_use]
112    pub fn timer4(&mut self) -> TIMER4_W<18> {
113        TIMER4_W::new(self)
114    }
115    #[doc = "Writes raw bits to the register."]
116    #[inline(always)]
117    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
118        self.0.bits(bits);
119        self
120    }
121}
122#[doc = "No Description\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clken1](index.html) module"]
123pub struct CLKEN1_SPEC;
124impl crate::RegisterSpec for CLKEN1_SPEC {
125    type Ux = u32;
126}
127#[doc = "`read()` method returns [clken1::R](R) reader structure"]
128impl crate::Readable for CLKEN1_SPEC {
129    type Reader = R;
130}
131#[doc = "`write(|w| ..)` method takes [clken1::W](W) writer structure"]
132impl crate::Writable for CLKEN1_SPEC {
133    type Writer = W;
134    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
135    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
136}
137#[doc = "`reset()` method sets CLKEN1 to value 0"]
138impl crate::Resettable for CLKEN1_SPEC {
139    const RESET_VALUE: Self::Ux = 0;
140}
efm32pg22_pac/efm32pg22c200/cmu_ns/clken1.rs

efm32pg22_pac/efm32pg22c200/cmu_ns/
clken1.rs
