efm32pg1b200_pac/ldma/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SYNCPRSSETEN` reader - Synchronization PRS Set Enable"]
38pub type SYNCPRSSETEN_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SYNCPRSSETEN` writer - Synchronization PRS Set Enable"]
40pub type SYNCPRSSETEN_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 8, 0>;
41#[doc = "Field `SYNCPRSCLREN` reader - Synchronization PRS Clear Enable"]
42pub type SYNCPRSCLREN_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `SYNCPRSCLREN` writer - Synchronization PRS Clear Enable"]
44pub type SYNCPRSCLREN_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 8, 8>;
45#[doc = "Field `NUMFIXED` reader - Number of Fixed Priority Channels"]
46pub type NUMFIXED_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `NUMFIXED` writer - Number of Fixed Priority Channels"]
48pub type NUMFIXED_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 3, 24>;
49impl R {
50    #[doc = "Bits 0:7 - Synchronization PRS Set Enable"]
51    #[inline(always)]
52    pub fn syncprsseten(&self) -> SYNCPRSSETEN_R {
53        SYNCPRSSETEN_R::new((self.bits & 0xff) as u8)
54    }
55    #[doc = "Bits 8:15 - Synchronization PRS Clear Enable"]
56    #[inline(always)]
57    pub fn syncprsclren(&self) -> SYNCPRSCLREN_R {
58        SYNCPRSCLREN_R::new(((self.bits >> 8) & 0xff) as u8)
59    }
60    #[doc = "Bits 24:26 - Number of Fixed Priority Channels"]
61    #[inline(always)]
62    pub fn numfixed(&self) -> NUMFIXED_R {
63        NUMFIXED_R::new(((self.bits >> 24) & 7) as u8)
64    }
65}
66impl W {
67    #[doc = "Bits 0:7 - Synchronization PRS Set Enable"]
68    #[inline(always)]
69    pub fn syncprsseten(&mut self) -> SYNCPRSSETEN_W {
70        SYNCPRSSETEN_W::new(self)
71    }
72    #[doc = "Bits 8:15 - Synchronization PRS Clear Enable"]
73    #[inline(always)]
74    pub fn syncprsclren(&mut self) -> SYNCPRSCLREN_W {
75        SYNCPRSCLREN_W::new(self)
76    }
77    #[doc = "Bits 24:26 - Number of Fixed Priority Channels"]
78    #[inline(always)]
79    pub fn numfixed(&mut self) -> NUMFIXED_W {
80        NUMFIXED_W::new(self)
81    }
82    #[doc = "Writes raw bits to the register."]
83    #[inline(always)]
84    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
85        self.0.bits(bits);
86        self
87    }
88}
89#[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
90pub struct CTRL_SPEC;
91impl crate::RegisterSpec for CTRL_SPEC {
92    type Ux = u32;
93}
94#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
95impl crate::Readable for CTRL_SPEC {
96    type Reader = R;
97}
98#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
99impl crate::Writable for CTRL_SPEC {
100    type Writer = W;
101}
102#[doc = "`reset()` method sets CTRL to value 0x0700_0000"]
103impl crate::Resettable for CTRL_SPEC {
104    #[inline(always)]
105    fn reset_value() -> Self::Ux {
106        0x0700_0000
107    }
108}
efm32pg1b200_pac/ldma/ctrl.rs

efm32pg1b200_pac/ldma/
ctrl.rs
