efm32pg1b200_pac/emu/
dcdctiming.rs

1#[doc = "Register `DCDCTIMING` reader"]
2pub struct R(crate::R<DCDCTIMING_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DCDCTIMING_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DCDCTIMING_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DCDCTIMING_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DCDCTIMING` writer"]
17pub struct W(crate::W<DCDCTIMING_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DCDCTIMING_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DCDCTIMING_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DCDCTIMING_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `LPINITWAIT` reader - Low Power Initialization Wait Time"]
38pub type LPINITWAIT_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `LPINITWAIT` writer - Low Power Initialization Wait Time"]
40pub type LPINITWAIT_W<'a> = crate::FieldWriter<'a, u32, DCDCTIMING_SPEC, u8, u8, 8, 0>;
41#[doc = "Field `COMPENPRCHGEN` reader - LN Mode Precharge Enable"]
42pub type COMPENPRCHGEN_R = crate::BitReader<bool>;
43#[doc = "Field `COMPENPRCHGEN` writer - LN Mode Precharge Enable"]
44pub type COMPENPRCHGEN_W<'a> = crate::BitWriter<'a, u32, DCDCTIMING_SPEC, bool, 11>;
45#[doc = "Field `LNWAIT` reader - Low Noise Controller Initialization Wait Time"]
46pub type LNWAIT_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `LNWAIT` writer - Low Noise Controller Initialization Wait Time"]
48pub type LNWAIT_W<'a> = crate::FieldWriter<'a, u32, DCDCTIMING_SPEC, u8, u8, 5, 12>;
49#[doc = "Field `BYPWAIT` reader - Bypass Mode Transition From Low Power or Low Noise Modes Wait Wait"]
50pub type BYPWAIT_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `BYPWAIT` writer - Bypass Mode Transition From Low Power or Low Noise Modes Wait Wait"]
52pub type BYPWAIT_W<'a> = crate::FieldWriter<'a, u32, DCDCTIMING_SPEC, u8, u8, 8, 20>;
53#[doc = "Field `DUTYSCALE` reader - Select Bias Duty Cycle Clock"]
54pub type DUTYSCALE_R = crate::FieldReader<u8, u8>;
55#[doc = "Field `DUTYSCALE` writer - Select Bias Duty Cycle Clock"]
56pub type DUTYSCALE_W<'a> = crate::FieldWriter<'a, u32, DCDCTIMING_SPEC, u8, u8, 2, 29>;
57impl R {
58    #[doc = "Bits 0:7 - Low Power Initialization Wait Time"]
59    #[inline(always)]
60    pub fn lpinitwait(&self) -> LPINITWAIT_R {
61        LPINITWAIT_R::new((self.bits & 0xff) as u8)
62    }
63    #[doc = "Bit 11 - LN Mode Precharge Enable"]
64    #[inline(always)]
65    pub fn compenprchgen(&self) -> COMPENPRCHGEN_R {
66        COMPENPRCHGEN_R::new(((self.bits >> 11) & 1) != 0)
67    }
68    #[doc = "Bits 12:16 - Low Noise Controller Initialization Wait Time"]
69    #[inline(always)]
70    pub fn lnwait(&self) -> LNWAIT_R {
71        LNWAIT_R::new(((self.bits >> 12) & 0x1f) as u8)
72    }
73    #[doc = "Bits 20:27 - Bypass Mode Transition From Low Power or Low Noise Modes Wait Wait"]
74    #[inline(always)]
75    pub fn bypwait(&self) -> BYPWAIT_R {
76        BYPWAIT_R::new(((self.bits >> 20) & 0xff) as u8)
77    }
78    #[doc = "Bits 29:30 - Select Bias Duty Cycle Clock"]
79    #[inline(always)]
80    pub fn dutyscale(&self) -> DUTYSCALE_R {
81        DUTYSCALE_R::new(((self.bits >> 29) & 3) as u8)
82    }
83}
84impl W {
85    #[doc = "Bits 0:7 - Low Power Initialization Wait Time"]
86    #[inline(always)]
87    pub fn lpinitwait(&mut self) -> LPINITWAIT_W {
88        LPINITWAIT_W::new(self)
89    }
90    #[doc = "Bit 11 - LN Mode Precharge Enable"]
91    #[inline(always)]
92    pub fn compenprchgen(&mut self) -> COMPENPRCHGEN_W {
93        COMPENPRCHGEN_W::new(self)
94    }
95    #[doc = "Bits 12:16 - Low Noise Controller Initialization Wait Time"]
96    #[inline(always)]
97    pub fn lnwait(&mut self) -> LNWAIT_W {
98        LNWAIT_W::new(self)
99    }
100    #[doc = "Bits 20:27 - Bypass Mode Transition From Low Power or Low Noise Modes Wait Wait"]
101    #[inline(always)]
102    pub fn bypwait(&mut self) -> BYPWAIT_W {
103        BYPWAIT_W::new(self)
104    }
105    #[doc = "Bits 29:30 - Select Bias Duty Cycle Clock"]
106    #[inline(always)]
107    pub fn dutyscale(&mut self) -> DUTYSCALE_W {
108        DUTYSCALE_W::new(self)
109    }
110    #[doc = "Writes raw bits to the register."]
111    #[inline(always)]
112    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
113        self.0.bits(bits);
114        self
115    }
116}
117#[doc = "DCDC Controller Timing Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcdctiming](index.html) module"]
118pub struct DCDCTIMING_SPEC;
119impl crate::RegisterSpec for DCDCTIMING_SPEC {
120    type Ux = u32;
121}
122#[doc = "`read()` method returns [dcdctiming::R](R) reader structure"]
123impl crate::Readable for DCDCTIMING_SPEC {
124    type Reader = R;
125}
126#[doc = "`write(|w| ..)` method takes [dcdctiming::W](W) writer structure"]
127impl crate::Writable for DCDCTIMING_SPEC {
128    type Writer = W;
129}
130#[doc = "`reset()` method sets DCDCTIMING to value 0x0ff1_f8ff"]
131impl crate::Resettable for DCDCTIMING_SPEC {
132    #[inline(always)]
133    fn reset_value() -> Self::Ux {
134        0x0ff1_f8ff
135    }
136}
efm32pg1b200_pac/emu/dcdctiming.rs

efm32pg1b200_pac/emu/
dcdctiming.rs
