efm32pg1b200_pac/cmu/
hfperclken0.rs

1#[doc = "Register `HFPERCLKEN0` reader"]
2pub struct R(crate::R<HFPERCLKEN0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HFPERCLKEN0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HFPERCLKEN0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HFPERCLKEN0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HFPERCLKEN0` writer"]
17pub struct W(crate::W<HFPERCLKEN0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HFPERCLKEN0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HFPERCLKEN0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HFPERCLKEN0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TIMER0` reader - Timer 0 Clock Enable"]
38pub type TIMER0_R = crate::BitReader<bool>;
39#[doc = "Field `TIMER0` writer - Timer 0 Clock Enable"]
40pub type TIMER0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 0>;
41#[doc = "Field `TIMER1` reader - Timer 1 Clock Enable"]
42pub type TIMER1_R = crate::BitReader<bool>;
43#[doc = "Field `TIMER1` writer - Timer 1 Clock Enable"]
44pub type TIMER1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 1>;
45#[doc = "Field `USART0` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
46pub type USART0_R = crate::BitReader<bool>;
47#[doc = "Field `USART0` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
48pub type USART0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 2>;
49#[doc = "Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
50pub type USART1_R = crate::BitReader<bool>;
51#[doc = "Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
52pub type USART1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 3>;
53#[doc = "Field `ACMP0` reader - Analog Comparator 0 Clock Enable"]
54pub type ACMP0_R = crate::BitReader<bool>;
55#[doc = "Field `ACMP0` writer - Analog Comparator 0 Clock Enable"]
56pub type ACMP0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 4>;
57#[doc = "Field `ACMP1` reader - Analog Comparator 1 Clock Enable"]
58pub type ACMP1_R = crate::BitReader<bool>;
59#[doc = "Field `ACMP1` writer - Analog Comparator 1 Clock Enable"]
60pub type ACMP1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 5>;
61#[doc = "Field `CRYOTIMER` reader - CRYOTIMER Clock Enable"]
62pub type CRYOTIMER_R = crate::BitReader<bool>;
63#[doc = "Field `CRYOTIMER` writer - CRYOTIMER Clock Enable"]
64pub type CRYOTIMER_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 6>;
65#[doc = "Field `I2C0` reader - I2C 0 Clock Enable"]
66pub type I2C0_R = crate::BitReader<bool>;
67#[doc = "Field `I2C0` writer - I2C 0 Clock Enable"]
68pub type I2C0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 7>;
69#[doc = "Field `ADC0` reader - Analog to Digital Converter 0 Clock Enable"]
70pub type ADC0_R = crate::BitReader<bool>;
71#[doc = "Field `ADC0` writer - Analog to Digital Converter 0 Clock Enable"]
72pub type ADC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 8>;
73#[doc = "Field `IDAC0` reader - Current Digital to Analog Converter 0 Clock Enable"]
74pub type IDAC0_R = crate::BitReader<bool>;
75#[doc = "Field `IDAC0` writer - Current Digital to Analog Converter 0 Clock Enable"]
76pub type IDAC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 9>;
77impl R {
78    #[doc = "Bit 0 - Timer 0 Clock Enable"]
79    #[inline(always)]
80    pub fn timer0(&self) -> TIMER0_R {
81        TIMER0_R::new((self.bits & 1) != 0)
82    }
83    #[doc = "Bit 1 - Timer 1 Clock Enable"]
84    #[inline(always)]
85    pub fn timer1(&self) -> TIMER1_R {
86        TIMER1_R::new(((self.bits >> 1) & 1) != 0)
87    }
88    #[doc = "Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
89    #[inline(always)]
90    pub fn usart0(&self) -> USART0_R {
91        USART0_R::new(((self.bits >> 2) & 1) != 0)
92    }
93    #[doc = "Bit 3 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
94    #[inline(always)]
95    pub fn usart1(&self) -> USART1_R {
96        USART1_R::new(((self.bits >> 3) & 1) != 0)
97    }
98    #[doc = "Bit 4 - Analog Comparator 0 Clock Enable"]
99    #[inline(always)]
100    pub fn acmp0(&self) -> ACMP0_R {
101        ACMP0_R::new(((self.bits >> 4) & 1) != 0)
102    }
103    #[doc = "Bit 5 - Analog Comparator 1 Clock Enable"]
104    #[inline(always)]
105    pub fn acmp1(&self) -> ACMP1_R {
106        ACMP1_R::new(((self.bits >> 5) & 1) != 0)
107    }
108    #[doc = "Bit 6 - CRYOTIMER Clock Enable"]
109    #[inline(always)]
110    pub fn cryotimer(&self) -> CRYOTIMER_R {
111        CRYOTIMER_R::new(((self.bits >> 6) & 1) != 0)
112    }
113    #[doc = "Bit 7 - I2C 0 Clock Enable"]
114    #[inline(always)]
115    pub fn i2c0(&self) -> I2C0_R {
116        I2C0_R::new(((self.bits >> 7) & 1) != 0)
117    }
118    #[doc = "Bit 8 - Analog to Digital Converter 0 Clock Enable"]
119    #[inline(always)]
120    pub fn adc0(&self) -> ADC0_R {
121        ADC0_R::new(((self.bits >> 8) & 1) != 0)
122    }
123    #[doc = "Bit 9 - Current Digital to Analog Converter 0 Clock Enable"]
124    #[inline(always)]
125    pub fn idac0(&self) -> IDAC0_R {
126        IDAC0_R::new(((self.bits >> 9) & 1) != 0)
127    }
128}
129impl W {
130    #[doc = "Bit 0 - Timer 0 Clock Enable"]
131    #[inline(always)]
132    pub fn timer0(&mut self) -> TIMER0_W {
133        TIMER0_W::new(self)
134    }
135    #[doc = "Bit 1 - Timer 1 Clock Enable"]
136    #[inline(always)]
137    pub fn timer1(&mut self) -> TIMER1_W {
138        TIMER1_W::new(self)
139    }
140    #[doc = "Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
141    #[inline(always)]
142    pub fn usart0(&mut self) -> USART0_W {
143        USART0_W::new(self)
144    }
145    #[doc = "Bit 3 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
146    #[inline(always)]
147    pub fn usart1(&mut self) -> USART1_W {
148        USART1_W::new(self)
149    }
150    #[doc = "Bit 4 - Analog Comparator 0 Clock Enable"]
151    #[inline(always)]
152    pub fn acmp0(&mut self) -> ACMP0_W {
153        ACMP0_W::new(self)
154    }
155    #[doc = "Bit 5 - Analog Comparator 1 Clock Enable"]
156    #[inline(always)]
157    pub fn acmp1(&mut self) -> ACMP1_W {
158        ACMP1_W::new(self)
159    }
160    #[doc = "Bit 6 - CRYOTIMER Clock Enable"]
161    #[inline(always)]
162    pub fn cryotimer(&mut self) -> CRYOTIMER_W {
163        CRYOTIMER_W::new(self)
164    }
165    #[doc = "Bit 7 - I2C 0 Clock Enable"]
166    #[inline(always)]
167    pub fn i2c0(&mut self) -> I2C0_W {
168        I2C0_W::new(self)
169    }
170    #[doc = "Bit 8 - Analog to Digital Converter 0 Clock Enable"]
171    #[inline(always)]
172    pub fn adc0(&mut self) -> ADC0_W {
173        ADC0_W::new(self)
174    }
175    #[doc = "Bit 9 - Current Digital to Analog Converter 0 Clock Enable"]
176    #[inline(always)]
177    pub fn idac0(&mut self) -> IDAC0_W {
178        IDAC0_W::new(self)
179    }
180    #[doc = "Writes raw bits to the register."]
181    #[inline(always)]
182    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
183        self.0.bits(bits);
184        self
185    }
186}
187#[doc = "High Frequency Peripheral Clock Enable Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfperclken0](index.html) module"]
188pub struct HFPERCLKEN0_SPEC;
189impl crate::RegisterSpec for HFPERCLKEN0_SPEC {
190    type Ux = u32;
191}
192#[doc = "`read()` method returns [hfperclken0::R](R) reader structure"]
193impl crate::Readable for HFPERCLKEN0_SPEC {
194    type Reader = R;
195}
196#[doc = "`write(|w| ..)` method takes [hfperclken0::W](W) writer structure"]
197impl crate::Writable for HFPERCLKEN0_SPEC {
198    type Writer = W;
199}
200#[doc = "`reset()` method sets HFPERCLKEN0 to value 0"]
201impl crate::Resettable for HFPERCLKEN0_SPEC {
202    #[inline(always)]
203    fn reset_value() -> Self::Ux {
204        0
205    }
206}
efm32pg1b200_pac/cmu/hfperclken0.rs

efm32pg1b200_pac/cmu/
hfperclken0.rs
