efm32pg1b200_pac/cmu/
dbgclksel.rs

1#[doc = "Register `DBGCLKSEL` reader"]
2pub struct R(crate::R<DBGCLKSEL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DBGCLKSEL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DBGCLKSEL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DBGCLKSEL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DBGCLKSEL` writer"]
17pub struct W(crate::W<DBGCLKSEL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DBGCLKSEL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DBGCLKSEL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DBGCLKSEL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Debug Trace Clock\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum DBG_A {
40    #[doc = "0: AUXHFRCO is the debug trace clock"]
41    AUXHFRCO = 0,
42    #[doc = "1: HFCLK is the debug trace clock"]
43    HFCLK = 1,
44}
45impl From<DBG_A> for bool {
46    #[inline(always)]
47    fn from(variant: DBG_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `DBG` reader - Debug Trace Clock"]
52pub type DBG_R = crate::BitReader<DBG_A>;
53impl DBG_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> DBG_A {
57        match self.bits {
58            false => DBG_A::AUXHFRCO,
59            true => DBG_A::HFCLK,
60        }
61    }
62    #[doc = "Checks if the value of the field is `AUXHFRCO`"]
63    #[inline(always)]
64    pub fn is_auxhfrco(&self) -> bool {
65        *self == DBG_A::AUXHFRCO
66    }
67    #[doc = "Checks if the value of the field is `HFCLK`"]
68    #[inline(always)]
69    pub fn is_hfclk(&self) -> bool {
70        *self == DBG_A::HFCLK
71    }
72}
73#[doc = "Field `DBG` writer - Debug Trace Clock"]
74pub type DBG_W<'a> = crate::BitWriter<'a, u32, DBGCLKSEL_SPEC, DBG_A, 0>;
75impl<'a> DBG_W<'a> {
76    #[doc = "AUXHFRCO is the debug trace clock"]
77    #[inline(always)]
78    pub fn auxhfrco(self) -> &'a mut W {
79        self.variant(DBG_A::AUXHFRCO)
80    }
81    #[doc = "HFCLK is the debug trace clock"]
82    #[inline(always)]
83    pub fn hfclk(self) -> &'a mut W {
84        self.variant(DBG_A::HFCLK)
85    }
86}
87impl R {
88    #[doc = "Bit 0 - Debug Trace Clock"]
89    #[inline(always)]
90    pub fn dbg(&self) -> DBG_R {
91        DBG_R::new((self.bits & 1) != 0)
92    }
93}
94impl W {
95    #[doc = "Bit 0 - Debug Trace Clock"]
96    #[inline(always)]
97    pub fn dbg(&mut self) -> DBG_W {
98        DBG_W::new(self)
99    }
100    #[doc = "Writes raw bits to the register."]
101    #[inline(always)]
102    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
103        self.0.bits(bits);
104        self
105    }
106}
107#[doc = "Debug Trace Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgclksel](index.html) module"]
108pub struct DBGCLKSEL_SPEC;
109impl crate::RegisterSpec for DBGCLKSEL_SPEC {
110    type Ux = u32;
111}
112#[doc = "`read()` method returns [dbgclksel::R](R) reader structure"]
113impl crate::Readable for DBGCLKSEL_SPEC {
114    type Reader = R;
115}
116#[doc = "`write(|w| ..)` method takes [dbgclksel::W](W) writer structure"]
117impl crate::Writable for DBGCLKSEL_SPEC {
118    type Writer = W;
119}
120#[doc = "`reset()` method sets DBGCLKSEL to value 0"]
121impl crate::Resettable for DBGCLKSEL_SPEC {
122    #[inline(always)]
123    fn reset_value() -> Self::Ux {
124        0
125    }
126}
efm32pg1b200_pac/cmu/dbgclksel.rs

efm32pg1b200_pac/cmu/
dbgclksel.rs
