efm32pg1b200_pac/adc0/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Warm-up Mode\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum WARMUPMODE_A {
41    #[doc = "0: ADC is shut down after each conversion. 5us warmup time is used before each conversion."]
42    NORMAL = 0,
43    #[doc = "1: ADC is kept in standby mode between conversions. 1us warmup time is used before each conversion."]
44    KEEPINSTANDBY = 1,
45    #[doc = "2: ADC is kept in slow acquisition mode between conversions. 1us warmup time is used before each conversion."]
46    KEEPINSLOWACC = 2,
47    #[doc = "3: ADC is kept on after conversions, allowing for continuous conversion."]
48    KEEPADCWARM = 3,
49}
50impl From<WARMUPMODE_A> for u8 {
51    #[inline(always)]
52    fn from(variant: WARMUPMODE_A) -> Self {
53        variant as _
54    }
55}
56#[doc = "Field `WARMUPMODE` reader - Warm-up Mode"]
57pub type WARMUPMODE_R = crate::FieldReader<u8, WARMUPMODE_A>;
58impl WARMUPMODE_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> WARMUPMODE_A {
62        match self.bits {
63            0 => WARMUPMODE_A::NORMAL,
64            1 => WARMUPMODE_A::KEEPINSTANDBY,
65            2 => WARMUPMODE_A::KEEPINSLOWACC,
66            3 => WARMUPMODE_A::KEEPADCWARM,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `NORMAL`"]
71    #[inline(always)]
72    pub fn is_normal(&self) -> bool {
73        *self == WARMUPMODE_A::NORMAL
74    }
75    #[doc = "Checks if the value of the field is `KEEPINSTANDBY`"]
76    #[inline(always)]
77    pub fn is_keepinstandby(&self) -> bool {
78        *self == WARMUPMODE_A::KEEPINSTANDBY
79    }
80    #[doc = "Checks if the value of the field is `KEEPINSLOWACC`"]
81    #[inline(always)]
82    pub fn is_keepinslowacc(&self) -> bool {
83        *self == WARMUPMODE_A::KEEPINSLOWACC
84    }
85    #[doc = "Checks if the value of the field is `KEEPADCWARM`"]
86    #[inline(always)]
87    pub fn is_keepadcwarm(&self) -> bool {
88        *self == WARMUPMODE_A::KEEPADCWARM
89    }
90}
91#[doc = "Field `WARMUPMODE` writer - Warm-up Mode"]
92pub type WARMUPMODE_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, WARMUPMODE_A, 2, 0>;
93impl<'a> WARMUPMODE_W<'a> {
94    #[doc = "ADC is shut down after each conversion. 5us warmup time is used before each conversion."]
95    #[inline(always)]
96    pub fn normal(self) -> &'a mut W {
97        self.variant(WARMUPMODE_A::NORMAL)
98    }
99    #[doc = "ADC is kept in standby mode between conversions. 1us warmup time is used before each conversion."]
100    #[inline(always)]
101    pub fn keepinstandby(self) -> &'a mut W {
102        self.variant(WARMUPMODE_A::KEEPINSTANDBY)
103    }
104    #[doc = "ADC is kept in slow acquisition mode between conversions. 1us warmup time is used before each conversion."]
105    #[inline(always)]
106    pub fn keepinslowacc(self) -> &'a mut W {
107        self.variant(WARMUPMODE_A::KEEPINSLOWACC)
108    }
109    #[doc = "ADC is kept on after conversions, allowing for continuous conversion."]
110    #[inline(always)]
111    pub fn keepadcwarm(self) -> &'a mut W {
112        self.variant(WARMUPMODE_A::KEEPADCWARM)
113    }
114}
115#[doc = "Field `SINGLEDMAWU` reader - SINGLEFIFO DMA Wakeup"]
116pub type SINGLEDMAWU_R = crate::BitReader<bool>;
117#[doc = "Field `SINGLEDMAWU` writer - SINGLEFIFO DMA Wakeup"]
118pub type SINGLEDMAWU_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 2>;
119#[doc = "Field `SCANDMAWU` reader - SCANFIFO DMA Wakeup"]
120pub type SCANDMAWU_R = crate::BitReader<bool>;
121#[doc = "Field `SCANDMAWU` writer - SCANFIFO DMA Wakeup"]
122pub type SCANDMAWU_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 3>;
123#[doc = "Field `TAILGATE` reader - Conversion Tailgating"]
124pub type TAILGATE_R = crate::BitReader<bool>;
125#[doc = "Field `TAILGATE` writer - Conversion Tailgating"]
126pub type TAILGATE_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 4>;
127#[doc = "Field `ASYNCCLKEN` reader - Selects ASYNC CLK Enable Mode When ADCCLKMODE=1"]
128pub type ASYNCCLKEN_R = crate::BitReader<bool>;
129#[doc = "Field `ASYNCCLKEN` writer - Selects ASYNC CLK Enable Mode When ADCCLKMODE=1"]
130pub type ASYNCCLKEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 6>;
131#[doc = "Field `ADCCLKMODE` reader - ADC Clock Mode"]
132pub type ADCCLKMODE_R = crate::BitReader<bool>;
133#[doc = "Field `ADCCLKMODE` writer - ADC Clock Mode"]
134pub type ADCCLKMODE_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 7>;
135#[doc = "Prescalar Setting for ADC Sample and Conversion Clock\n\nValue on reset: 0"]
136#[derive(Clone, Copy, Debug, PartialEq)]
137#[repr(u8)]
138pub enum PRESC_A {
139    #[doc = "0: `0`"]
140    NODIVISION = 0,
141}
142impl From<PRESC_A> for u8 {
143    #[inline(always)]
144    fn from(variant: PRESC_A) -> Self {
145        variant as _
146    }
147}
148#[doc = "Field `PRESC` reader - Prescalar Setting for ADC Sample and Conversion Clock"]
149pub type PRESC_R = crate::FieldReader<u8, PRESC_A>;
150impl PRESC_R {
151    #[doc = "Get enumerated values variant"]
152    #[inline(always)]
153    pub fn variant(&self) -> Option<PRESC_A> {
154        match self.bits {
155            0 => Some(PRESC_A::NODIVISION),
156            _ => None,
157        }
158    }
159    #[doc = "Checks if the value of the field is `NODIVISION`"]
160    #[inline(always)]
161    pub fn is_nodivision(&self) -> bool {
162        *self == PRESC_A::NODIVISION
163    }
164}
165#[doc = "Field `PRESC` writer - Prescalar Setting for ADC Sample and Conversion Clock"]
166pub type PRESC_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, PRESC_A, 7, 8>;
167impl<'a> PRESC_W<'a> {
168    #[doc = "`0`"]
169    #[inline(always)]
170    pub fn nodivision(self) -> &'a mut W {
171        self.variant(PRESC_A::NODIVISION)
172    }
173}
174#[doc = "Field `TIMEBASE` reader - 1us Time Base"]
175pub type TIMEBASE_R = crate::FieldReader<u8, u8>;
176#[doc = "Field `TIMEBASE` writer - 1us Time Base"]
177pub type TIMEBASE_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 7, 16>;
178#[doc = "Oversample Rate Select\n\nValue on reset: 0"]
179#[derive(Clone, Copy, Debug, PartialEq)]
180#[repr(u8)]
181pub enum OVSRSEL_A {
182    #[doc = "0: 2 samples for each conversion result"]
183    X2 = 0,
184    #[doc = "1: 4 samples for each conversion result"]
185    X4 = 1,
186    #[doc = "2: 8 samples for each conversion result"]
187    X8 = 2,
188    #[doc = "3: 16 samples for each conversion result"]
189    X16 = 3,
190    #[doc = "4: 32 samples for each conversion result"]
191    X32 = 4,
192    #[doc = "5: 64 samples for each conversion result"]
193    X64 = 5,
194    #[doc = "6: 128 samples for each conversion result"]
195    X128 = 6,
196    #[doc = "7: 256 samples for each conversion result"]
197    X256 = 7,
198    #[doc = "8: 512 samples for each conversion result"]
199    X512 = 8,
200    #[doc = "9: 1024 samples for each conversion result"]
201    X1024 = 9,
202    #[doc = "10: 2048 samples for each conversion result"]
203    X2048 = 10,
204    #[doc = "11: 4096 samples for each conversion result"]
205    X4096 = 11,
206}
207impl From<OVSRSEL_A> for u8 {
208    #[inline(always)]
209    fn from(variant: OVSRSEL_A) -> Self {
210        variant as _
211    }
212}
213#[doc = "Field `OVSRSEL` reader - Oversample Rate Select"]
214pub type OVSRSEL_R = crate::FieldReader<u8, OVSRSEL_A>;
215impl OVSRSEL_R {
216    #[doc = "Get enumerated values variant"]
217    #[inline(always)]
218    pub fn variant(&self) -> Option<OVSRSEL_A> {
219        match self.bits {
220            0 => Some(OVSRSEL_A::X2),
221            1 => Some(OVSRSEL_A::X4),
222            2 => Some(OVSRSEL_A::X8),
223            3 => Some(OVSRSEL_A::X16),
224            4 => Some(OVSRSEL_A::X32),
225            5 => Some(OVSRSEL_A::X64),
226            6 => Some(OVSRSEL_A::X128),
227            7 => Some(OVSRSEL_A::X256),
228            8 => Some(OVSRSEL_A::X512),
229            9 => Some(OVSRSEL_A::X1024),
230            10 => Some(OVSRSEL_A::X2048),
231            11 => Some(OVSRSEL_A::X4096),
232            _ => None,
233        }
234    }
235    #[doc = "Checks if the value of the field is `X2`"]
236    #[inline(always)]
237    pub fn is_x2(&self) -> bool {
238        *self == OVSRSEL_A::X2
239    }
240    #[doc = "Checks if the value of the field is `X4`"]
241    #[inline(always)]
242    pub fn is_x4(&self) -> bool {
243        *self == OVSRSEL_A::X4
244    }
245    #[doc = "Checks if the value of the field is `X8`"]
246    #[inline(always)]
247    pub fn is_x8(&self) -> bool {
248        *self == OVSRSEL_A::X8
249    }
250    #[doc = "Checks if the value of the field is `X16`"]
251    #[inline(always)]
252    pub fn is_x16(&self) -> bool {
253        *self == OVSRSEL_A::X16
254    }
255    #[doc = "Checks if the value of the field is `X32`"]
256    #[inline(always)]
257    pub fn is_x32(&self) -> bool {
258        *self == OVSRSEL_A::X32
259    }
260    #[doc = "Checks if the value of the field is `X64`"]
261    #[inline(always)]
262    pub fn is_x64(&self) -> bool {
263        *self == OVSRSEL_A::X64
264    }
265    #[doc = "Checks if the value of the field is `X128`"]
266    #[inline(always)]
267    pub fn is_x128(&self) -> bool {
268        *self == OVSRSEL_A::X128
269    }
270    #[doc = "Checks if the value of the field is `X256`"]
271    #[inline(always)]
272    pub fn is_x256(&self) -> bool {
273        *self == OVSRSEL_A::X256
274    }
275    #[doc = "Checks if the value of the field is `X512`"]
276    #[inline(always)]
277    pub fn is_x512(&self) -> bool {
278        *self == OVSRSEL_A::X512
279    }
280    #[doc = "Checks if the value of the field is `X1024`"]
281    #[inline(always)]
282    pub fn is_x1024(&self) -> bool {
283        *self == OVSRSEL_A::X1024
284    }
285    #[doc = "Checks if the value of the field is `X2048`"]
286    #[inline(always)]
287    pub fn is_x2048(&self) -> bool {
288        *self == OVSRSEL_A::X2048
289    }
290    #[doc = "Checks if the value of the field is `X4096`"]
291    #[inline(always)]
292    pub fn is_x4096(&self) -> bool {
293        *self == OVSRSEL_A::X4096
294    }
295}
296#[doc = "Field `OVSRSEL` writer - Oversample Rate Select"]
297pub type OVSRSEL_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, OVSRSEL_A, 4, 24>;
298impl<'a> OVSRSEL_W<'a> {
299    #[doc = "2 samples for each conversion result"]
300    #[inline(always)]
301    pub fn x2(self) -> &'a mut W {
302        self.variant(OVSRSEL_A::X2)
303    }
304    #[doc = "4 samples for each conversion result"]
305    #[inline(always)]
306    pub fn x4(self) -> &'a mut W {
307        self.variant(OVSRSEL_A::X4)
308    }
309    #[doc = "8 samples for each conversion result"]
310    #[inline(always)]
311    pub fn x8(self) -> &'a mut W {
312        self.variant(OVSRSEL_A::X8)
313    }
314    #[doc = "16 samples for each conversion result"]
315    #[inline(always)]
316    pub fn x16(self) -> &'a mut W {
317        self.variant(OVSRSEL_A::X16)
318    }
319    #[doc = "32 samples for each conversion result"]
320    #[inline(always)]
321    pub fn x32(self) -> &'a mut W {
322        self.variant(OVSRSEL_A::X32)
323    }
324    #[doc = "64 samples for each conversion result"]
325    #[inline(always)]
326    pub fn x64(self) -> &'a mut W {
327        self.variant(OVSRSEL_A::X64)
328    }
329    #[doc = "128 samples for each conversion result"]
330    #[inline(always)]
331    pub fn x128(self) -> &'a mut W {
332        self.variant(OVSRSEL_A::X128)
333    }
334    #[doc = "256 samples for each conversion result"]
335    #[inline(always)]
336    pub fn x256(self) -> &'a mut W {
337        self.variant(OVSRSEL_A::X256)
338    }
339    #[doc = "512 samples for each conversion result"]
340    #[inline(always)]
341    pub fn x512(self) -> &'a mut W {
342        self.variant(OVSRSEL_A::X512)
343    }
344    #[doc = "1024 samples for each conversion result"]
345    #[inline(always)]
346    pub fn x1024(self) -> &'a mut W {
347        self.variant(OVSRSEL_A::X1024)
348    }
349    #[doc = "2048 samples for each conversion result"]
350    #[inline(always)]
351    pub fn x2048(self) -> &'a mut W {
352        self.variant(OVSRSEL_A::X2048)
353    }
354    #[doc = "4096 samples for each conversion result"]
355    #[inline(always)]
356    pub fn x4096(self) -> &'a mut W {
357        self.variant(OVSRSEL_A::X4096)
358    }
359}
360#[doc = "Field `CHCONMODE` reader - Channel Connect"]
361pub type CHCONMODE_R = crate::BitReader<bool>;
362#[doc = "Field `CHCONMODE` writer - Channel Connect"]
363pub type CHCONMODE_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 29>;
364impl R {
365    #[doc = "Bits 0:1 - Warm-up Mode"]
366    #[inline(always)]
367    pub fn warmupmode(&self) -> WARMUPMODE_R {
368        WARMUPMODE_R::new((self.bits & 3) as u8)
369    }
370    #[doc = "Bit 2 - SINGLEFIFO DMA Wakeup"]
371    #[inline(always)]
372    pub fn singledmawu(&self) -> SINGLEDMAWU_R {
373        SINGLEDMAWU_R::new(((self.bits >> 2) & 1) != 0)
374    }
375    #[doc = "Bit 3 - SCANFIFO DMA Wakeup"]
376    #[inline(always)]
377    pub fn scandmawu(&self) -> SCANDMAWU_R {
378        SCANDMAWU_R::new(((self.bits >> 3) & 1) != 0)
379    }
380    #[doc = "Bit 4 - Conversion Tailgating"]
381    #[inline(always)]
382    pub fn tailgate(&self) -> TAILGATE_R {
383        TAILGATE_R::new(((self.bits >> 4) & 1) != 0)
384    }
385    #[doc = "Bit 6 - Selects ASYNC CLK Enable Mode When ADCCLKMODE=1"]
386    #[inline(always)]
387    pub fn asyncclken(&self) -> ASYNCCLKEN_R {
388        ASYNCCLKEN_R::new(((self.bits >> 6) & 1) != 0)
389    }
390    #[doc = "Bit 7 - ADC Clock Mode"]
391    #[inline(always)]
392    pub fn adcclkmode(&self) -> ADCCLKMODE_R {
393        ADCCLKMODE_R::new(((self.bits >> 7) & 1) != 0)
394    }
395    #[doc = "Bits 8:14 - Prescalar Setting for ADC Sample and Conversion Clock"]
396    #[inline(always)]
397    pub fn presc(&self) -> PRESC_R {
398        PRESC_R::new(((self.bits >> 8) & 0x7f) as u8)
399    }
400    #[doc = "Bits 16:22 - 1us Time Base"]
401    #[inline(always)]
402    pub fn timebase(&self) -> TIMEBASE_R {
403        TIMEBASE_R::new(((self.bits >> 16) & 0x7f) as u8)
404    }
405    #[doc = "Bits 24:27 - Oversample Rate Select"]
406    #[inline(always)]
407    pub fn ovsrsel(&self) -> OVSRSEL_R {
408        OVSRSEL_R::new(((self.bits >> 24) & 0x0f) as u8)
409    }
410    #[doc = "Bit 29 - Channel Connect"]
411    #[inline(always)]
412    pub fn chconmode(&self) -> CHCONMODE_R {
413        CHCONMODE_R::new(((self.bits >> 29) & 1) != 0)
414    }
415}
416impl W {
417    #[doc = "Bits 0:1 - Warm-up Mode"]
418    #[inline(always)]
419    pub fn warmupmode(&mut self) -> WARMUPMODE_W {
420        WARMUPMODE_W::new(self)
421    }
422    #[doc = "Bit 2 - SINGLEFIFO DMA Wakeup"]
423    #[inline(always)]
424    pub fn singledmawu(&mut self) -> SINGLEDMAWU_W {
425        SINGLEDMAWU_W::new(self)
426    }
427    #[doc = "Bit 3 - SCANFIFO DMA Wakeup"]
428    #[inline(always)]
429    pub fn scandmawu(&mut self) -> SCANDMAWU_W {
430        SCANDMAWU_W::new(self)
431    }
432    #[doc = "Bit 4 - Conversion Tailgating"]
433    #[inline(always)]
434    pub fn tailgate(&mut self) -> TAILGATE_W {
435        TAILGATE_W::new(self)
436    }
437    #[doc = "Bit 6 - Selects ASYNC CLK Enable Mode When ADCCLKMODE=1"]
438    #[inline(always)]
439    pub fn asyncclken(&mut self) -> ASYNCCLKEN_W {
440        ASYNCCLKEN_W::new(self)
441    }
442    #[doc = "Bit 7 - ADC Clock Mode"]
443    #[inline(always)]
444    pub fn adcclkmode(&mut self) -> ADCCLKMODE_W {
445        ADCCLKMODE_W::new(self)
446    }
447    #[doc = "Bits 8:14 - Prescalar Setting for ADC Sample and Conversion Clock"]
448    #[inline(always)]
449    pub fn presc(&mut self) -> PRESC_W {
450        PRESC_W::new(self)
451    }
452    #[doc = "Bits 16:22 - 1us Time Base"]
453    #[inline(always)]
454    pub fn timebase(&mut self) -> TIMEBASE_W {
455        TIMEBASE_W::new(self)
456    }
457    #[doc = "Bits 24:27 - Oversample Rate Select"]
458    #[inline(always)]
459    pub fn ovsrsel(&mut self) -> OVSRSEL_W {
460        OVSRSEL_W::new(self)
461    }
462    #[doc = "Bit 29 - Channel Connect"]
463    #[inline(always)]
464    pub fn chconmode(&mut self) -> CHCONMODE_W {
465        CHCONMODE_W::new(self)
466    }
467    #[doc = "Writes raw bits to the register."]
468    #[inline(always)]
469    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
470        self.0.bits(bits);
471        self
472    }
473}
474#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
475pub struct CTRL_SPEC;
476impl crate::RegisterSpec for CTRL_SPEC {
477    type Ux = u32;
478}
479#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
480impl crate::Readable for CTRL_SPEC {
481    type Reader = R;
482}
483#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
484impl crate::Writable for CTRL_SPEC {
485    type Writer = W;
486}
487#[doc = "`reset()` method sets CTRL to value 0x001f_0000"]
488impl crate::Resettable for CTRL_SPEC {
489    #[inline(always)]
490    fn reset_value() -> Self::Ux {
491        0x001f_0000
492    }
493}
efm32pg1b200_pac/adc0/ctrl.rs

efm32pg1b200_pac/adc0/
ctrl.rs
